SLOSE75B Data sheet

SLOSE75B February 2022 – March 2023 TAS2780

PRODUCTION DATA

Package Options

Mechanical Data (Package|Pins)

RYA|30
- MPQF601

Thermal pad, mechanical data (Package|Pins)

Orderable Information

6.5 Electrical Characteristics

T_A = 25 °C, PVDD = 18 V, VBAT1S = 3.8 V, AVDD = 1.8V, IOVDD =1.8 V, R_L = 4Ω + 15µH, f_in = 1 kHz, f_s = 48 kHz, Gain = 21 dBV, SDZ = 1, NG_EN=0, EN_LLSR=0, PWR_MODE1⁽²⁾, measured filter free as in Section 7 (unless otherwise noted).

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
DIGITAL INPUT and OUTPUT
V_IH	High-level digital input logic voltage threshold	All digital pins	0.7×IOVDD			V
V_IL	Low-level digital input logic voltage threshold	All digital pins			0.3 × IOVDD	V
V_OH	High-level digital output voltage	All digital pins except SDA, SCL, IRQZ, BYP_EN; I_OH = 100 µA.	IOVDD–0.2V			V
V_OL	Low-level digital output voltage	All digital pins except SDA, SCL,IRQZ, BY_EN; I_OL = –100 µA.			0.2	V
V_OL(I2C)	Low-level digital output voltage	SDA and SCL; I_OL = -1 mA.			0.2 x IOVDD	V
V_OL(IRQZ)	Low-level digital output voltage for IRQZ and BY_EN open drain outputs	IRQZ, BY_EN; I_OL = -1 mA.			0.2	V
I_IH	Input logic-high leakage for digital inputs	All digital pins; Input = Supply Rail.	–1		1	µA
I_IL	Input logic-low leakage for digital inputs	All digital pins; Input = GND.	–1		1	µA
C_IN	Input capacitance for digital inputs	All digital pins		5		pF
R_PD	Pull down resistance for IO pins when asserted on			18		kΩ
R_OS	OUT to VSNS resistors	Load disconnected		10		kΩ
IO	Output Current Strength	Measured at 0.4 V below supply and 0.4 V above GND.		8		mA
AMPLIFIER PERFORMANCE
P_OUT	Peak Output Power	THD+N = 10 %, VBAT1S = 5 V, PWR_MODE0⁽¹⁾, PWR_MODE1⁽²⁾		30		W
P_OUT	Maximum Continuous Output Power	THD+N = 1 %, VBAT1S= 5 V, PWR_MODE0, PWR_MODE1		25		W
	System Efficiency	P_OUT = 1 W, VBAT1S= 5 V, PWR_MODE1		85		%
		P_OUT = 1 W, VBAT1S= 5 V, PWR_MODE0		79
		P_OUT = 3 W, VBAT1S= 5 V, PWR_MODE0 and PWR_MODE1		85
		P_OUT = 8 W, VBAT1S = 5 V, PWR_MODE0 and PWR_MODE1		88
THD+N	Total Harmonic Distortion and Noise	P_OUT = 1 W		-84		dB
THD+N	Total Harmonic Distortion and Noise	P_OUT = 1 W, f_in = 6.667 kHz		-84		dB
IMD	Inter-Modulation Distortion	ITU-R, 19 kHz / 20 kHz, 1: 1: 12.5 W		-83		dB
V_N	Idle Channel Noise	A-Weighted, 20 Hz - 20 kHz, PWR_MODE0		40		µV
		A-Weighted, 20 Hz - 20 kHz, PWR_MODE2 ⁽³⁾		34
		A-Weighted, 20 Hz - 20k Hz, PWR_MODE1		32
	Idle Channel Noise with Ultrasonic Chirp (100 us duty cycle, 25 ms period)	A-Weighted, 20 Hz - 20 kHz, VBAT1S = 5 V, PWR_MODE3 ⁽⁴⁾, 1 V_Peak, Register 0x73 set to E0h		34
F_PWM	Class-D PWM Switching Frequency	Average frequency in Spread Spectrum Mode, CLASSD_SYNC=0		384		kHz
		Fixed Frequency Mode, CLASSD_SYNC=0		384
		Fixed Frequency Mode, CLASSD_SYNC=1, f_s = 44.1, 88.2 kHz		352.8
		Fixed Frequency Mode, CLASSD_SYNC=1, f_s = 48, 96 kHz		384
V_OS	Output Offset Voltage	Idle Mode	-1.3	±0.33	1.3	mV
DNR	Dynamic Range	A-Weighted, -60 dBFS		110		dB
		A-Weighted, -60 dBFS, PWR_MODE2		109
		A-Weighted, -60 dBFS, PWR_MODE0		109
SNR	Signal to Noise Ratio	A-Weighted, Referenced to 1 % THD+N Output Level		110		dB
		A-Weighted, Referenced to 1 % THD+N Output Level, PWR_MODE2		110
		A-Weighted, Referenced to 1 % THD+N Output Level, PWR_MODE0		109
K_CP	Click and Pop Performance	Idle mode, Into and out of Shutdown, A-weighted		0.8		mV
	Full Scale Output Voltage	f_s ≤ 48 kHz		21		dBV
	Minimum Programmable Gain	f_s ≤ 48 kHz		11		dBV
	Maximum Programmable Gain	f_s ≤ 48 kHz		21		dBV
	Programmable Output Level Step Size			0.5		dB
	Mute attenuation	Device in Software Shutdown or Muted in Normal Operation		108		dB
	Chip to Chip Group Delay		-1		1	µs
	PVDD Power Supply Rejection Ratio	PVDD = 18 V + 200 mV_pp, f_ripple = 217 Hz		118		dB
		PVDD = 18 V + 200 mV_pp, f_ripple = 1 kHz		110
		PVDD = 18 V + 200 mV_pp, f_ripple = 20 kHz		95
	VBAT1S Power Supply Rejection Ratio	VBAT1S = 3.8 V + 200 mV_pp, f_ripple = 217 Hz		114		dB
		VBAT1S = 3.8 V + 200 mV_pp, f_ripple = 1 kHz		110
		VBAT1S = 3.8 V + 200 mV_pp, f_ripple = 20 kHz		90
	AVDD Power Supply Rejection Ratio	AVDD = 1.8 V + 200 mV_pp, f_ripple = 217 Hz		105		dB
		AVDD = 1.8 V + 200 mV_pp, f_ripple = 1 kHz		104
		AVDD = 1.8 V + 200 mV_pp, f_ripple = 20 kHz		87
	Power Supply Inter-modulation	PVDD, 217 Hz, 100-mVpp, Input f=1kHz @ 400 mW		-120		dB
		VBAT1S,217 Hz, 100-mVpp, Input f=1kHz @ 400 mW		-120
		AVDD, 217 Hz, 100-mVpp, Input f = 1 kHz @ 400 mW		-80
		IOVDD 217 Hz, 100-mVpp, Input f = 1 kHz @ 400 mW		-120
	Turn ON Time from Release of SW Shutdown	No Volume Ramping		1.12		ms
	Turn ON Time from Release of SW Shutdown	Volume Ramping		6.7		ms
	Turn OFF Time from Assertion of SW Shutdown to Amp Hi-Z	No Volume Ramping		0.56		ms
	Turn OFF Time from Assertion of SW Shutdown to Amp Hi-Z	Volume Ramping		6		ms
	Out of HW Shutdown to First I²C command		1			ms
DIAGNOSTIC GENERATOR
THD+N	Total Harmonic Distortion and Noise	Pout = 1 W		-82		dB
f_err	Frequency Error	Using internal oscillator: DG_CLK = 0		2		%
DIE TEMPERATURE SENSOR
	Resolution			8		bits
	Minimum Temperature Measurement Range			-40		°C
	Maximum Temperature Measurement Range			150		°C
	Die Temperature Resolution			1		°C
	Die Temperature Accuracy		-5		5	°C
VOLTAGE MONITOR
	Resolution			12		bits
	PVDD Measurement Range	Minimum Level		2		V
	PVDD Measurement Range	Maximum Level		23		V
	PVDD Resolution			22.5		mV
	PVDD Accuracy	2 V ≤ PVDDV ≤ 23 V		±60		mV
	VBAT1S Measurement Range	Minimum Level		2		V
	VBAT1S Measurement Range	Maximum Level		6		V
	VBAT1S Resolution			20		mV
	VBAT1S Accuracy	2.3 V ≤ VBAT1S ≤ 6 V		±20		mV
TDM SERIAL AUDIO PORT
	Minimum PCM Sample Rates and FSYNC Input Frequency			44.1		kHz
	Maximum PCM Sample Rates and FSYNC Input Frequency			96		kHz
	Minimum SBCLK Input Frequency	I²S/TDM Operation		0.7056		MHz
	Maximum SBCLK Input Frequency	I²S/TDM Operation		24.576		MHz
	SBCLK Maximum Input Jitter	RMS Jitter below 40 kHz that can be tolerated without performance degradation			0.5	ns
	SBCLK Maximum Input Jitter	RMS Jitter above 40 kHz that can be tolerated without performance degradation			1	ns
	Minimum SBCLK Cycles per FSYNC in I²S and TDM Modes	Other Values: 24, 32, 48, 64, 96, 125, 128, 192, 250, 256, 384, 500		16		Cycles
	Maximum SBCLK Cycles per FSYNC in I²S and TDM Modes	Other Values: 24, 32, 48, 64, 96, 125, 128, 192, 250, 256, 384, 500		512		Cycles
PCM PLAYBACK CHARACTERISTICS f_s ≤ 48 kHz
f_s	Minimum Sample Rate			44.1		kHz
f_s	Maximum Sample Rate			48		kHz
	Frequency for Passband Ripple			0.454		f_s
	Passband Ripple	20 Hz to LPF cutoff frequency	-0.15		0.15	dB
	Stop Band Attenuation	≥ 0.55 f_s		60		dB
	Stop Band Attenuation	≥ 1 f_s		65		dB
	Group Delay (Including Noise Gate)	DC to 0.454 f_s, DC blocker disabled		19		1/f_s
PCM PLAYBACK CHARACTERISTICS f_s > 48 kHz
fs	Minimum Sample Rates			88.2		kHz
fs	Maximum Sample Rate			96		kHz
	Frequency for Passband Ripple	f_s = 96 kHz		0.437		f_s
	Passband 3db Frequency	f_s = 96 kHz		0.459		f_s
	Passband Ripple	DC to LPF cutoff frequency	-0.5		0.5	dB
	Stop Band Attenuation	≥ 0.56 f_s		60		dB
	Stop Band Attenuation	≥ 1 f_s		65		dB
	Group Delay (Including Noise Gate)	DC to 0.375 f_s for 96 kHz, DC blocker disabled		35		1/f_s
SPEAKER CURRENT SENSE
	Resolution			16		bits
DNR	Dynamic Range	Un-weighted, relative to 0 dBFS.		70		dB
THD+N	Total Harmonic Distortion and Noise	Pout = 15 W		-64		dB
	Full Scale Input Current	Measured at -6 dBFS. Re-scaled at 0 dBFS.		5		A
	Differential Mode Gain		0.98		1.02
	Frequency Response	20 Hz - 20 kHz	-0.1		0.1	dB
	Group Delay			5		1/f_s
SPEAKER VOLTAGE SENSE
	Resolution			16		bits
DNR	Dynamic Range	Un-Weighted, Relative 0 dBFS		75		dB
THD+N	Total Harmonic Distortion and Noise	Pout = 15 W		-71		dB
	Full Scale Input Voltage			16		V_PK
	Differential Mode Gain		0.98		1.02
	Frequency Response	20 Hz - 20 kHz	-0.1		0.1	dB
	Group Delay			5		1/f_s
SPEAKER VOLTAGE/CURRENT SENSE RATIO
	Gain Linearity	Pout ≥ 40 mW to 0.1% THD+N, using a 40 Hz -40 dBFS pilot tone, PWR_MODE0 and PWR_MODE1	-1		1	%
	Gain error over temperature	-20°C to 70°C, Pout = 1 W		±0.6		%
	Phase Error between V and I			300		ns
PROTECTION CIRCUITRY
	Brownout Prevention Latency to First Attack	BOP_SRC=1		19		µs
	Thermal Shutdown Temperature			142		°C
	Thermal Shutdown Retry	OTE_RETRY=1		1.5		s
	Output Over Current Limit on PVDD	Output to Output, Output to GND or Output to PVDD Short	5.5	6.6		A
	Output Over Current Limit on VBAT1S	Output to Output, Output to GND or Output to VBAT1S Short	2	2.6		A
	VBAT1S Undervoltage Lockout Threshold	UVLO is asserted		2		V
	VBAT1S Undervoltage Lockout Threshold	UVLO is de-asserted		2.16		V
	AVDD Undervoltage Lockout Threshold	UVLO is asserted		1.45		V
	AVDD Undervoltage Lockout Threshold	UVLO is de-asserted		1.51		V
	IOVDD Undervoltage Lockout Threshold	UVLO is asserted		1.13		V
	IOVDD Undervoltage Lockout Threshold	UVLO is de-asserted		1.25		V
	VBAT1S Internal LDO Undervoltage Lockout Threshold	UVLO is asserted	4			V
TYPICAL CURRENT CONSUMPTION
	Hardware Shutdown	SDZ = 0, PVDD		0.05		µA
		SDZ = 0, VBAT1S		0.01
		SDZ = 0, AVDD		0.14
		SDZ = 0, IOVDD		0.005
	Software Shutdown	All Clocks Stopped, PVDD		0.05		µA
		All Clocks Stopped, VBAT1S		0.5
		All Clocks Stopped, AVDD		10.2
		All Clocks Stopped, IOVDD		0.55
						mA
	Noise Gate Mode	f_s = 48 kHz, PVDD		0.012
		f_s = 48 kHz, VBAT1S		0.13
		f_s = 48 kHz, AVDD		3
		f_s = 48 kHz, IOVDD		0.01
	Idle Mode - PWR_MODE1	f_s = 48 kHz, PVDD		0.04		mA
		f_s = 48 kHz, VBAT1S		2.2
		f_s = 48 kHz, AVDD, IV Sense = Enabled		9.2
		f_s = 48 kHz, AVDD, IV Sense = Disabled		6.8
		f_s = 48 kHz, IOVDD		0.02
	Idle Mode - PWR_MODE2	f_s = 48 kHz, PVDD		3		mA
		f_s = 48 kHz, AVDD, IV Sense = Enabled		9.2
		f_s = 48 kHz, AVDD, IV Sense = Disabled		6.8
		f_s = 48 kHz, IOVDD		0.02
	Idle Mode - PWR_MODE0	f_s = 48 kHz, PVDD		2.28		mA
		f_s = 48 kHz, VBAT1S		2.1
		f_s = 48 kHz, AVDD, IV Sense = Enabled		9.2
		f_s = 48 kHz, AVDD, IV Sense = Disabled		6.8
		f_s = 48 kHz, IOVDD		0.02

(1) PWR_MODE0: CDS_MODE=10, VBAT1S_MODE=0

(2) PWR_MODE1: CDS_MODE=00, VBAT1S_MODE=0

(3) PWR_MODE2: CDS_MODE=11, VBAT1S_MODE=1

(4) PWR_MODE3: CDS_MODE=01, VBAT1S_MODE=0