SLASFD8 May   2025 TAS5830

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Typical Characteristics
      1. 5.7.1 Bridge Tied Load (BTL) Configuration Curves with BD Modulation
      2. 5.7.2 Bridge Tied Load (BTL) Configuration Curves with 1SPW Modulation
      3. 5.7.3 Parallel Bridge Tied Load (PBTL) Configuration With BD Modulation
      4. 5.7.4 Parallel Bridge Tied Load (PBTL) Configuration With 1SPW Modulation
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Power Supplies
      2. 6.3.2 Device Clocking
      3. 6.3.3 Serial Audio Port – Clock Rates
      4. 6.3.4 Clock Halt Auto-recovery
      5. 6.3.5 Sample Rate on the Fly Change
      6. 6.3.6 Serial Audio Port - Data Formats and Bit Depths
    4. 6.4 Device Functional Modes
      1. 6.4.1 Software Control
      2. 6.4.2 Speaker Amplifier Operating Modes
        1. 6.4.2.1 BTL Mode
        2. 6.4.2.2 PBTL Mode
      3. 6.4.3 Low EMI Modes
        1. 6.4.3.1 Spread Spectrum
        2. 6.4.3.2 Channel to Channel Phase Shift
        3. 6.4.3.3 Multi-Devices PWM Phase Synchronization
          1. 6.4.3.3.1 Phase Synchronization With I2S Clock In Startup Phase
          2. 6.4.3.3.2 Phase Synchronization With GPIO
      4. 6.4.4 Thermal Foldback
      5. 6.4.5 Device State Control
      6. 6.4.6 Device Modulation
        1. 6.4.6.1 BD Modulation
        2. 6.4.6.2 1SPW Modulation
        3. 6.4.6.3 Hybrid Modulation
      7. 6.4.7 Programming and Control
        1. 6.4.7.1 I2C Serial Communication Bus
        2. 6.4.7.2 Hardware Control Mode
        3. 6.4.7.3 I2C Target Address
          1. 6.4.7.3.1 Random Write
          2. 6.4.7.3.2 Sequential Write
          3. 6.4.7.3.3 Random Read
          4. 6.4.7.3.4 Sequential Read
          5. 6.4.7.3.5 DSP Memory Book, Page and BQ update
          6. 6.4.7.3.6 Checksum
            1. 6.4.7.3.6.1 Cyclic Redundancy Check (CRC) Checksum
            2. 6.4.7.3.6.2 Exclusive or (XOR) Checksum
        4. 6.4.7.4 Control via Software
          1. 6.4.7.4.1 Startup Procedures
          2. 6.4.7.4.2 Shutdown Procedures
        5. 6.4.7.5 Protection and Monitoring
          1. 6.4.7.5.1 Overcurrent Limit (Cycle-By-Cycle)
          2. 6.4.7.5.2 Overcurrent Shutdown (OCSD)
          3. 6.4.7.5.3 DC Detect Error
          4. 6.4.7.5.4 Overtemperature Shutdown (OTSD)
          5. 6.4.7.5.5 PVDD Overvoltage and Undervoltage Error
          6. 6.4.7.5.6 PVDD Drop Detection
          7. 6.4.7.5.7 Clock Fault
  8. 7 Register Maps
    1. 7.1 reg_map Registers
  9. 8 Application and Implementation
    1. 8.1 Typical Applications
      1. 8.1.1 2.0 (Stereo BTL) System
      2. 8.1.2 Mono (PBTL) Systems
    2. 8.2 Power Supply Recommendations
      1. 8.2.1 DVDD Supply
      2. 8.2.2 PVDD Supply
    3. 8.3 Layout
      1. 8.3.1 Layout Guidelines
        1. 8.3.1.1 General Guidelines for Audio Amplifiers
        2. 8.3.1.2 Importance of PVDD Bypass Capacitor Placement on PVDD Network
        3. 8.3.1.3 Optimizing Thermal Performance
      2. 8.3.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Device Nomenclature
      2. 9.1.2 Development Support
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.4.7.2 Hardware Control Mode

For systems that do not require the advanced flexibility of the I2C registers control or does not have an available I2C host controller, the TAS5830 can be used in Hardware Control Mode. Then the device operates in Hardware mode default configurations and any change is accomplished via the Hardware control pins. The audio performance between Hardware and Software Control modes with the same configuration is identical, however, more features are accessible under Software Control Mode through registers.

Several I/O's on the TAS5830 needs to be taken into consideration during schematic design for desired start up settings. The method for going into Hardware Control Mode is to pull high HW_MODE pin 8 to DVDD.

The TAS5830 default Hardware configuration is BTL mode, 768kHz switching frequency, 1SPW mode, 175kHz Class D amplifier loop bandwidth, 29.5Vp/FS analog gain, CBC threshold with 80% of OCP threshold. It requires the HW_SEL0 pin 16 and HW_SEL1 pin 15 directly tied to GND.

Table 6-3 Hardware Control - HW_SEL0 Pin16
Pin Configuration Analog Gain H-Bridge Output Configuration
0Ω to GND 33.1VP/FS BTL
1kΩ to GND 23.4VP/FS BTL
4.7kΩ to GND 16.6VP/FS BTL
15kΩ to GND 8.3VP/FS BTL
33kΩ to DVDD 8.3VP/FS PBTL
6.8kΩ to DVDD 16.6VP/FS PBTL
1.5kΩ to DVDD 23.4VP/FS PBTL
0Ω to DVDD 33.1VP/FS PBTL
Table 6-4 Hardware Control - HW_SEL1 Pin15
Pin ConfigurationFSW&Class D Loop BandwidthCycle By Cycle Current Limit Threshold Spread SpectrumModulation
0Ω to GND768kHz FSW, 175kHz BWCBC Threshold = 80% OCPDisable1SPW
1kΩ to GND768kHz FSW, 175kHz BWCBC DisableDisable1SPW
4.7kΩ to GND768kHz FSW, 175kHz BWCBC Threshold = 40% OCPDisable1SPW
15kΩ to GND768kHz FSW, 175kHz BWCBC Threshold = 60% OCPDisable1SPW
33kΩ to DVDD480kHz FSW, 100kHz BWCBC DisableEnableBD
6.8kΩ to DVDD480kHz FSW, 100kHz BWCBC Threshold = 80% OCPEnableBD
1.5kΩ to DVDD480kHz FSW, 100kHz BWCBC Threshold = 40% OCPEnableBD
0Ω to DVDD480kHz FSW, 100kHz BWCBC Threshold = 60% OCPEnableBD

Example 1:

BTL Mode, FSW = 768kHz, 1SPW Modulation, 175kHz Loop Bandwidth, CBC Threshold = 80% OCP, Analog Gain = 29.5VP/FS, Spread spectrum disabled.


TAS5830 Typical Hardware Control Mode Application Schematic-BTL Mode
Figure 6-10 Typical Hardware Control Mode Application Schematic-BTL Mode

Example 2:

PBTL Mode, FSW = 768kHz, 1 SPW Modulation, 175kHz Loop Bandwidth, CBC Threshold = 80% OCP, Analog Gain = 29.5VP/FS, Spread spectrum disabled.


TAS5830 Typical Hardware Control Mode Application Schematic-PBTL Mode
Figure 6-11 Typical Hardware Control Mode Application Schematic-PBTL Mode