SLASFD8 May   2025 TAS5830

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Typical Characteristics
      1. 5.7.1 Bridge Tied Load (BTL) Configuration Curves with BD Modulation
      2. 5.7.2 Bridge Tied Load (BTL) Configuration Curves with 1SPW Modulation
      3. 5.7.3 Parallel Bridge Tied Load (PBTL) Configuration With BD Modulation
      4. 5.7.4 Parallel Bridge Tied Load (PBTL) Configuration With 1SPW Modulation
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Power Supplies
      2. 6.3.2 Device Clocking
      3. 6.3.3 Serial Audio Port – Clock Rates
      4. 6.3.4 Clock Halt Auto-recovery
      5. 6.3.5 Sample Rate on the Fly Change
      6. 6.3.6 Serial Audio Port - Data Formats and Bit Depths
    4. 6.4 Device Functional Modes
      1. 6.4.1 Software Control
      2. 6.4.2 Speaker Amplifier Operating Modes
        1. 6.4.2.1 BTL Mode
        2. 6.4.2.2 PBTL Mode
      3. 6.4.3 Low EMI Modes
        1. 6.4.3.1 Spread Spectrum
        2. 6.4.3.2 Channel to Channel Phase Shift
        3. 6.4.3.3 Multi-Devices PWM Phase Synchronization
          1. 6.4.3.3.1 Phase Synchronization With I2S Clock In Startup Phase
          2. 6.4.3.3.2 Phase Synchronization With GPIO
      4. 6.4.4 Thermal Foldback
      5. 6.4.5 Device State Control
      6. 6.4.6 Device Modulation
        1. 6.4.6.1 BD Modulation
        2. 6.4.6.2 1SPW Modulation
        3. 6.4.6.3 Hybrid Modulation
      7. 6.4.7 Programming and Control
        1. 6.4.7.1 I2C Serial Communication Bus
        2. 6.4.7.2 Hardware Control Mode
        3. 6.4.7.3 I2C Target Address
          1. 6.4.7.3.1 Random Write
          2. 6.4.7.3.2 Sequential Write
          3. 6.4.7.3.3 Random Read
          4. 6.4.7.3.4 Sequential Read
          5. 6.4.7.3.5 DSP Memory Book, Page and BQ update
          6. 6.4.7.3.6 Checksum
            1. 6.4.7.3.6.1 Cyclic Redundancy Check (CRC) Checksum
            2. 6.4.7.3.6.2 Exclusive or (XOR) Checksum
        4. 6.4.7.4 Control via Software
          1. 6.4.7.4.1 Startup Procedures
          2. 6.4.7.4.2 Shutdown Procedures
        5. 6.4.7.5 Protection and Monitoring
          1. 6.4.7.5.1 Overcurrent Limit (Cycle-By-Cycle)
          2. 6.4.7.5.2 Overcurrent Shutdown (OCSD)
          3. 6.4.7.5.3 DC Detect Error
          4. 6.4.7.5.4 Overtemperature Shutdown (OTSD)
          5. 6.4.7.5.5 PVDD Overvoltage and Undervoltage Error
          6. 6.4.7.5.6 PVDD Drop Detection
          7. 6.4.7.5.7 Clock Fault
  8. 7 Register Maps
    1. 7.1 reg_map Registers
  9. 8 Application and Implementation
    1. 8.1 Typical Applications
      1. 8.1.1 2.0 (Stereo BTL) System
      2. 8.1.2 Mono (PBTL) Systems
    2. 8.2 Power Supply Recommendations
      1. 8.2.1 DVDD Supply
      2. 8.2.2 PVDD Supply
    3. 8.3 Layout
      1. 8.3.1 Layout Guidelines
        1. 8.3.1.1 General Guidelines for Audio Amplifiers
        2. 8.3.1.2 Importance of PVDD Bypass Capacitor Placement on PVDD Network
        3. 8.3.1.3 Optimizing Thermal Performance
      2. 8.3.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Device Nomenclature
      2. 9.1.2 Development Support
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5.5 Electrical Characteristics

Free-air room temperature 25°C, 1SPW Mode, LC filter=10uH+0.68uF, Fsw=384kHz, Class D Bandwidth=80kHz, (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Digital I/O
|IIH| Input logic high current level
for DVDD referenced digital
input pins		 VIN(DigIn) = VDVDD 10 uA
|IIL| Input logic low current level
for DVDD referenced digital
input pins		 VIN(DigIn) = 0 V –10 uA
VIH(Digin) Input logic high threshold for
DVDD referenced digital
inputs		 70% VDVDD
VIL(Digin) Input logic low threshold for
DVDD referenced digital
inputs		 30% VDVDD
VOH(Digin) Output logic high voltage
level		 IOH = 4 mA 80% VDVDD
VOL(Digin) Output logic low voltage level IOH = –4 mA 20% VDVDD
I2C CONTROL PORT
CL(I2C) Allowable load capacitance
for each I2C Line		 400 pF
fSCL(fast) Support SCL frequency No wait states, fast mode 400 1000 kHz
fSCL(slow) Support SCL frequency No wait states, slow mode 100 kHz
SERIAL AUDIO PORT
tDLY Required LRCLK/FS to SCLK
rising edge delay		 5 ns
DSCLK Allowable SCLK duty cycle 40% 60%
fS Supported input sample rates 32 192 kHz
fSCLK Supported SCLK frequencies 32 64 fS
fSCLK SCLK frequency 24.576 MHz
AMPLIFIER OPERATING MODE AND DC PRAMETERS
toff Turn-off Time Play to Shutdown, HiZ, Sleep, or Deep Sleep. Excluding volume ramp. 4.35 ms
twake Wake up time Deep sleep to Play. Excluding volume ramp.  2.4 ms
twake Wake up time Sleep to Play. Excluding volume ramp.  2.3 ms
twake Wake up time Hi-Z to Play. Excluding volume ramp.  70 µs
ICC Quiescent supply current of
DVDD		 PDN = 2 V, DVDD = 3.3 V, Play mode,
General Audio Process flow with full DSP running		 24 mA
ICC Quiescent supply current of
DVDD		 PDN = 2 V, DVDD = 3.3 V, Sleep mode 1 mA
ICC Quiescent supply current of
DVDD		 PDN = 2 V, DVDD = 3.3 V, Deep Sleep mode 1 mA
ICC Quiescent supply current of
DVDD		 PDN = 0.8 V, DVDD = 3.3 V, Shutdown mode 18 uA
ICC Quiescent supply current of
PVDD		 PDN = 2 V, PVDD = 24 V, No Load, LC filter =
10 μH + 0.68 μF, FSW = 384 kHz, 1SPW Modulation, Play Mode		 35 mA
ICC Quiescent supply current of
PVDD		 PDN = 2 V, PVDD = 24 V, No Load, LC filter =
10 μH + 0.68 μF, FSW = 384 kHz, Output Hiz Mode		 11 mA
ICC Quiescent supply current of
PVDD		 PDN = 2 V, PVDD = 24 V, No Load, LC filter =
10 μH + 0.68 μF, FSW = 384 kHz, Sleep Mode		 7.5 mA
ICC Quiescent supply current of
PVDD		 PDN = 2 V, PVDD = 24 V, No Load, LC filter =
10 μH + 0.68 μF, FSW = 384 kHz, Deep Sleep Mode		 10 uA
ICC Quiescent supply current of
PVDD		 PDN = 2 V, PVDD = 24 V, No Load, LC filter =
10 μH + 0.68 μF, FSW = 384 kHz, Shutdown Mode		 10 uA
AV(SPK_AMP) Programmable Gain Value represents the "peak voltage" disregarding
clipping due to lower PVDD
Measured at 0 dB input(1FS)		 14.9 30.4 dBV
ΔAV(SPK_AMP) Amplifier gain error Gain = 30.4dBV 0.5 dB
fSPK_AMP Switching frequency of the
speaker amplifier. 		 Software Mode 384 kHz
fSPK_AMP Switching frequency of the
speaker amplifier. 		 Software Mode 480 kHz
fSPK_AMP Switching frequency of the
speaker amplifier. 		 Software Mode 576 kHz
fSPK_AMP Switching frequency of the
speaker amplifier. 		 Software Mode 768 kHz
fSPK_AMP Switching frequency of the
speaker amplifier. 		 Hardware Mode 480 kHz
fSPK_AMP Switching frequency of the
speaker amplifier. 		 Hardware Mode 768 kHz
RDS(on) Drain-to-source on resistance
of the individual output
MOSFETs		 FET + Metallization. VPVDD = 24V, I(OUT) = 500mA,
TJ=25℃		 70 mΩ
Efficiency(BTL) The efficiency of low power playing(Power stage efficiency) PVDD = 24V, LC filter = 10 μH + 0.68 μF, FSW = 384 kHz, 1SPW Modulation, Load = 4Ω, playing 1W output power on each channel 53 %
Efficiency(PBTL) The efficiency of larger power playing(Power stage efficiency) PVDD = 24V, LC filter = 10 μH + 0.68 μF, FSW = 384 kHz, 1SPW Modulation, Load = 3Ω, playing 120W output power 92 %
PROTECTION
OCETHRES Over-Current Error Threshold
(Speaker current)		 Speaker Output Current (Post LC filter), Speaker
current, LC Filter=10uH+0.68uF, BTL Mode		 7.5 8 8.5 A
UVETHRES(PVDD) PVDD under voltage error
threshold		 4 4.25 V
OVETHRES(PVDD) PVDD over voltage error
threshold		 30.5 32 V
DCETHRES Output DC Error protection
threshold		 Class D Amplifier's output DC voltage cross
speaker load to trigger Output DC Fault protection		 3.2 V
TDCDET Output DC Detect time Class D Amplifier's output remain at or above
DCETHRES		 640 ms
OTETHRES Over temperature error
threshold		 179 ℃
OTEHystersis Over temperature error
hysteresis		 11 ℃
OTWTHRES Over temperature warning
level		 Read by register 0x73 bit0 106 °C
OTWTHRES Over temperature warning
level		 Read by register 0x73 bit1 130 °C
OTWTHRES Over temperature warning
level		 Read by register 0x73 bit2 143 °C
OTWTHRES Over temperature warning
level		 Read by register 0x73 bit3 156 °C
AUDIO PERFORMACNE (STEREO BTL)
|VOS| Amplifier offset voltage Measured differentially with zero input data,
programmable gain configured with 30.4dBV
analog gain, VPVDD range: 12V~30V		 –5 5 mV
THD+NSPK Total harmonic distortion and
noise
(PO = 1 W, f = 1 KHz)		 VPVDD = 26V, LC Filter = 10uH + 0.68uF, Load = 4Ω 0.015 %
VPVDD = 26V, LC Filter = 10uH + 0.68uF, Load = 8Ω 0.015 %
PO(SPK) Output Power (Per Channel) VPVDD = 26V,  LC Filter = 10uH + 0.68uF, RSPK = 4Ω, f = 1kHz, THD+N = 10% 80 W
PO(SPK) Output Power (Per Channel) VPVDD = 26V, LC Filter = 10uH + 0.68uF, RSPK = 4Ω, f = 1kHz, THD+N = 1% 65 W
PO(SPK) Output Power (Per Channel) VPVDD = 26V, LC Filter = 10uH + 0.68uF, RSPK = 8Ω, f = 1kHz, THD+N = 10% 41 W
PO(SPK) Output Power (Per Channel) VPVDD = 26V, LC Filter = 10uH + 0.68uF, RSPK = 8 Ω, f = 1kHz, THD+N = 1% 33 W
ICN(SPK) Idle channel noise(Aweighted,
AES17)		 VPVDD = 26V, LC Filter = 10uH + 0.68uF, Load = 4Ω, Fsw = 576kHz, BD Modulation 40 µVrms
VPVDD = 26V, LC Filter = 10uH + 0.68uF, Load = 4Ω, Fsw = 384kHz, 1SPW Modulation 37 µVrms
VPVDD = 26V, LC Filter = 10uH + 0.68uF, Load = 8Ω, Fsw = 576kHz, BD Modulation 42 µVrms
VPVDD = 26V, LC Filter = 10uH + 0.68uF, Load = 8Ω, Fsw = 384kHz, 1SPW Modulation 40 µVrms
DR Dynamic range A-Weighted, -60 dBFS method. VPVDD = 24V, Load = 6Ω Analog Gain = 30.4dBV 111 dB
SNR Signal-to-noise ratio A-Weighted, referenced to 1% THD+N Output Level, VPVDD = 24V, Load = 6Ω 111 dB
A-Weighted, referenced to 1% THD+N Output Level, VPVDD = 18V, Load = 4Ω 108 dB
PSRR Power supply rejection ratio Injected Noise = 1kHz, 1Vrms, VPVDD = 26V, Input audio signal = digital zero 73 dB
X-talkSPK Cross-talk (worst case
between left-to-right and
right-to-left coupling)		 f = 1kHz, based on Inductor (DFEG7030D-4R7)
from Murata		 100 dB
AUDIO PERFORMANCE (MONO PBTL)
|VOS| Amplifier offset voltage Measured differentially with zero input data,
programmable gain configured with 30.4dBV
Analog gain, VPVDD = 12V-30V range,  1SPW mode		 –5 5 mV
PO(SPK) Output Power VPVDD = 29V, RSPK = 3Ω, f = 1kHz, THD+N = 1% 123 W
VPVDD = 29V, RSPK = 3Ω, f = 1kHz, THD+N = 10% 148 W
VPVDD = 24V, RSPK = 2Ω, f = 1kHz, THD+N = 1% 119 W
VPVDD = 24V, RSPK = 2Ω, f = 1kHz, THD+N = 10% 141 W
THD+NSPK Total harmonic distortion and
noise
(PO = 1 W, f = 1 KHz)		 VPVDD = 24V, LC-filter = 10uH + 0.68uF, RSPK = 2Ω 0.05 %
VPVDD = 29V, LC-filter = 10uH + 0.68uF, RSPK = 3Ω 0.07 %
DR Dynamic range A-Weighted, -60 dBFS method, VPVDD = 29V, RSPK
= 3Ω.		 109 dB
SNR Signal-to-noise ratio A-Weighted, referenced to 1% THD+N Output
Level, VPVDD = 29V, RSPK = 3Ω		 109 dB
A-Weighted,referenced to 1% THD+N Output
Level, VPVDD = 24V, RSPK = 2Ω		 108 dB
PSRR Power supply rejection ratio Injected Noise = 1kHz, 1Vrms, VPVDD = 18V,
input audio signal = digital zero		 70 dB