SNLS697A April 2021 – February 2023 TDES954
PRODUCTION DATA
RX port specific register. The V3Link Port Select register 0x4C configures which unique RX port registers can be accessed by I2C read and write commands.
BIT | FIELD | TYPE | DEFAULT | DESCRIPTION |
---|---|---|---|---|
7 | CSI_WAIT_FS1 | R/W | 0x0 | CSI Wait for FrameStart packet with count 1 The CSI Receiver will wait for a Frame Start packet with count of 1 before accepting other packets |
6 | CSI_WAIT_FS | R/W | 0x1 | CSI Wait for FrameStart packet CSI-2 Receiver will wait for a Frame Start packet before accepting other packets |
5 | CSI_FWD_CKSUM | R/W | 0x1 | Forward CSI packets with checksum errors 0: Do not forward packets with errors 1: Forward packets with errors |
4 | CSI_FWD_ECC | R/W | 0x1 | Forward CSI packets with ECC errors 0: Do not forward packets with errors 1: Forward packets with errors |
3 | CSI_FWD_LEN/ DISCARD_1ST _LINE_ON_ERR |
R/W | 0x1 | In CSI V3Link Input Mode, Forward CSI
packets with length errors. In RAW Input Mode, forward truncated 1st
video line. 0: CSI: Do not forward packets with errors. RAW: Forward truncated 1st video line 1: CSI: Forward packets with errors. RAW: Discard truncated 1st video line |
2 | COAX_MODE | R/W | S | Enable coax cable mode Default value set by strap condition of MODE pin upon asserting PDB = HIGH at start-up. 0: Shielded-twisted pair (STP) mode 1: Coax mode |
1:0 | V3LINK_MODE | R/W | S | V3Link Input Mode Default value set by strap condition of MODE pin upon asserting PDB = HIGH at start-up. 00: CSI Mode (TSER953 compatible) 01: RAW12 Mode/50 MHz (DVP Mode serializer compatible) 10: RAW12 Mode/75 MHz (DVP Mode serializer compatible) 11: RAW10 Mode/100 MHz (DVP Mode serializer compatible) |