SNLS697A April 2021 – February 2023 TDES954
PRODUCTION DATA
RX port specific register. The V3Link Port Select register 0x4C configures which unique RX port registers can be accessed by I2C read and write commands.
BIT | FIELD | TYPE | DEFAULT | DESCRIPTION |
---|---|---|---|---|
7 | LINE_LEN _UNSTABLE | R/RC | 0x0 | Line Length Unstable If set, this bit indicates the line length was detected as unstable during a previous video frame. The line length is considered to be stable if all the lines in the video frame have the same length. This flag will remain set until read. |
6 | LINE_LEN_CHG | R/RC | 0x0 | Line Length Changed 1: Change of line length detected 0: Change of line length not detected This bit is cleared on read. |
5 | V3LINK_ENCODE _ERROR | R/RC | 0x0 | V3Link Encoder error detected If set, this flag indicates an error in the V3Link encoding has been detected by the V3Link receiver. This bit is cleared on read. Note, to detect V3LINK Encoder errors, the LINK_ERROR_COUNT must be enabled with a LINK_ERR_THRESH value greater than 1. Otherwise, the loss of Receiver Lock will prevent detection of the Encoder error. |
4 | BUFFER_ERROR | R/RC | 0x0 | Packet buffer error detected. If this bit is set, an overflow condition has occurred on the packet buffer FIFO. 1: Packet Buffer error detected 0: No Packet Buffer errors detected This bit is cleared on read. |
3 | CSI_ERROR | R | 0x0 | CSI Receive error detected. See the CSI_RX_STS register for details. |
2 | FREQ_STABLE | R | 0x0 | Frequency measurement stable |
1 | CABLE_FAULT | R | 0x0 | When link is expected to be operational, CABLE_FAULT would indicate open or short on the cable as no V3Link clock is detected at the deserializer Rx input. |
0 | LINE_CNT_CHG | R/RC | 0x0 | Line Count Changed 1: Change of line count detected 0: Change of line count not detected This bit is cleared on read. |