Product details


Function Deserializer Input compatibility V3Link Output compatibility MIPI CSI-2 Color depth (bpp) 24 Pixel clock frequency (Min) (MHz) 25 Pixel clock frequency (Max) (MHz) 100 Throughput (Mbps) 6656 Rating Catalog Features Line Fault Detection, Flexible GPIOs, Coax or STP, Ultra-Low Data and Control Path Latency, CRC, Pattern Generation, Internal Programmable Precision Frame Sync Generator Signal conditioning Adaptive Equalizer, Programmable Equalizer EMI reduction LVDS Diagnostics BIST Operating temperature range (C) -20 to 85 open-in-new Find other Camera SerDes

Package | Pins | Size

VQFN (RGZ) 48 49 mm² 7 x 7 open-in-new Find other Camera SerDes


  • Dual deserializer hub aggregates one or two active sensors over V3Link interface
  • Device temperature range: –20℃ to +85℃ TA
  • Power-over-coax (PoC) compatible transceiver
  • MIPI DPHY version 1.2 / CSI-2 version 1.3 compliant:
    • CSI-2 output ports
    • Supports 1, 2, 3, 4 data lanes
    • CSI-2 data rate scalable for 400 Mbps / 800 Mbps / 1.5 Gbps / 1.6 Gbps each data lane
    • Programmable data types
    • Four virtual channels
    • ECC and CRC generation
  • Ultra-low data and control path latency
  • Supports single-ended coaxial or shielded twisted-pair (STP) cable
  • Adaptive receive equalization
  • I2C with fast-mode plus up to 1 Mbps
  • Flexible GPIOs for camera synchronization and diagnostics
  • Compatible with TSER953 serializer
  • Line fault detection and advanced diagnostics
  • IEC 61000-4-2 ESD compliant

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The TDES954 is a versatile dual deserializer hub capable of receiving serialized sensor data from one or two independent sources through a V3Link interface. When paired with a TSER953 serializer, the TDES954 receives data from imagers, supporting 2MP/60fps and 4MP/30fps cameras as well as satellite RADAR and other sensors such as ToF and LIDAR. Data is received and aggregated into a MIPI CSI-2 compliant output for interconnect to a downstream processor. For sensors with DVP Mode serializers, the TDES954 receives and aggregates data from one or two sensors including Full HD 1080p 2MP 60/fps imager sensors. When configuring the CSI-2 interface for 2-lane operation, a duplicate MIPI CSI-2 clock lane is available to provide a replicated output. Replication mode creates two copies of the aggregated video stream for data logging and parallel processing.

The TDES954 and partner TSER953 chipset is designed to receive data across either 50-Ω single-ended coaxial or 100-Ω differential STP cables. The deserializer hub is ideal for Power-over-Coax applications and the receive equalizer automatically adapts to compensate for cable loss characteristics with no additional programming required, including cable degradation over time.

Each V3Link interface includes a separate low latency bidirectional control channel (BCC) that continuously conveys I2C, GPIO, and other control information. GPIO signals purposed for sensor synchronization and diagnostic features also make use of the BCC.

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Technical documentation

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Type Title Date
* Data sheet TDES954 Dual 4.16 Gbps V3Link Deserializer Hub With MIPI CSI-2 Interface for High Speed, High Resolution Cameras, RADAR, and Other Sensors datasheet Apr. 25, 2021
Technical article How to choose a power supply for an automotive camera module Sep. 17, 2020

Design & development

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Hardware development

document-generic User guide

The Texas Instruments DS90UB954-Q1EVM Evaluation Module (EVM) is a functional board design for evaluating the DS90UB954-Q1 FPD-Link III deserializer hub, which converts serialized sensor data to MIPI CSI-2 for processing. It is configured for communication with up to two DS90UB953-Q1 or DS90UB933-Q1 (...)

  • Aggregates data from up to 2 cameras over FPD-Link III interface
  • Supports 2-Megapixel sensors with HD 1080p resolution at 30/60Hz frame rate (when paired with DS90UB953-Q1)
  • Supports MIPI DPHY 1.2 / CSI-2 Version 1.3 compliant
  • Supports single-ended coax cable and power-over-coax
  • On-board I2C programming (...)

Design tools & simulation

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PSpice® for TI design and simulation tool
PSPICE-FOR-TI — PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
  • Leverages Cadence PSpice Technology
  • Preinstalled library with a suite of digital models to enable worst-case timing analysis
  • Dynamic updates ensure you have access to most current device models
  • Optimized for simulation speed without loss of accuracy
  • Supports simultaneous analysis of multiple products
  • (...)
SPICE-based analog simulation program
TINA-TI TINA-TI provides all the conventional DC, transient and frequency domain analysis of SPICE and much more. TINA has extensive post-processing capability that allows you to format results the way you want them. Virtual instruments allow you to select input waveforms and probe circuit nodes voltages (...)
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