SNLS697A April 2021 – February 2023 TDES954
PRODUCTION DATA
BIT | FIELD | TYPE | DEFAULT | DESCRIPTION |
---|---|---|---|---|
7:6 | BIST_OUT_MODE | R/W | 0x0 | BIST Output Mode 00 : Outputs disabled during BIST 01 : Reserved 10 : Outputs enabled during BIST 11 : Reserved |
5:4 | RESERVED | R/W | 0x0 | Reserved |
3 | BIST_PIN_CONFIG | R/W | 0x1 | Bist Configured through Pin. 1: Bist configured through pin. 0: Bist configured through bits 2:0 in this register |
2:1 | BIST_CLOCK _SOURCE | R/W | 0x00 | BIST Clock Source This register field selects the BIST Clock Source at the Serializer. These register bits are automatically written to the CLOCK SOURCE bits (register offset 0x14) in the Serializer after BIST is enabled. See the appropriate Serializer register descriptions for details. When connected to a DVP Mode serializer, a setting of 0x3 may result in a clock frequency that is too slow for proper recovery. |
0 | BIST_EN | R/W | 0x0 | BIST Control 1: Enabled 0: Disabled |