SLOS080W September   1978  – July 2025 TL071 , TL071A , TL071B , TL071H , TL072 , TL072A , TL072B , TL072H , TL072M , TL074 , TL074A , TL074B , TL074H , TL074M

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information for Single Channel
    5. 5.5  Thermal Information for Dual Channel
    6. 5.6  Thermal Information for Quad Channel
    7. 5.7  Electrical Characteristics for TL07xH
    8. 5.8  Electrical Characteristics (DC) for TL07xC, TL07xAC, TL07xBC, TL07xI, TL07xM
    9. 5.9  Electrical Characteristics (AC) for TL07xC, TL07xAC, TL07xBC, TL07xI, TL07xM
    10. 5.10 Typical Characteristics: TL07xH
    11. 5.11 Typical Characteristics: All Devices Except TL07xH
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Total Harmonic Distortion
      2. 7.3.2 Slew Rate
    4. 7.4 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Inverting Amplifier
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curve
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Device Nomenclature
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • D|8
  • P|8
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5.7 Electrical Characteristics for TL07xH

at VS = (VCC+) – (VCC–) = 4.5 V to 40 V (±2.25 V to ±20 V), TA = 25°C, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and VOUT = VS / 2 (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
OFFSET VOLTAGE
VOS Input offset voltage ±1 ±4 mV
TA = –40°C to +125°C ±5
dVOS/dT Input offset voltage drift TA = –40°C to +125°C ±2 µV/℃
PSRR Input offset voltage versus power supply VS = 5 V to 40 V, 
VCM = VS / 2		 TA = –40°C to +125°C ±1 ±10 μV/V
Channel separation f = 0 Hz 10 µV/V
INPUT BIAS CURRENT
IB Input bias current  ±1 ±120 pA
DCK and DBV packages ±1 ±300 pA
TA = –40°C to +125°C(1) ±5 nA
IOS Input offset current  ±0.5 ±120 pA
DCK and DBV packages ±0.5 ±250 pA
TA = –40°C to +125°C(1) ±5 nA
NOISE
EN Input voltage noise f = 0.1 Hz to 10 Hz   9.2 μVPP
  1.4   µVRMS
eN Input voltage noise density f = 1 kHz 37   nV/√Hz
f = 10 kHz   21  
iN Input current noise f = 1 kHz   80 fA/√Hz
INPUT VOLTAGE RANGE
VCM Common-mode voltage (VCC–) + 1.5 (VCC+) V
CMRR Common-mode rejection ratio VS = 40 V, (VCC–) + 2.5 V < VCM < (VCC+) – 1.5 V 100 105 dB
TA = –40°C to +125°C 95 dB
VS = 40 V, (VCC–) + 2.5 V < VCM < (VCC+) 90 105 dB
TA = –40°C to +125°C 80 dB
INPUT CAPACITANCE
ZID Differential 100 || 2 MΩ || pF
ZICM Common-mode 6 || 1 TΩ || pF
OPEN-LOOP GAIN
AOL Open-loop voltage gain VS = 40 V, VCM = VS / 2,
(VCC–) + 0.3 V < VO < (VCC+) –  0.3 V		 TA = –40°C to +125°C 118 125 dB
AOL Open-loop voltage gain VS = 40 V, VCM = VS / 2,
RL = 2 kΩ, (VCC–) + 1.2 V < VO < (VCC+) –  1.2 V		 TA = –40°C to +125°C 115 120 dB
FREQUENCY RESPONSE
GBW Gain-bandwidth product 5.25 MHz
SR Slew rate VS = 40 V, G = +1, CL = 20 pF 20 V/μs
tS Settling time To 0.1%, VS = 40 V, VSTEP = 10 V , G = +1, CL = 20 pF 0.63 μs
To 0.1%, VS = 40 V, VSTEP = 2 V , G = +1, CL = 20 pF 0.56
To 0.01%, VS = 40 V, VSTEP = 10 V , G = +1, CL = 20 pF 0.91
To 0.01%, VS = 40 V, VSTEP = 2 V , G = +1, CL = 20 pF 0.48
Phase margin G = +1, RL = 10kΩ, CL = 20 pF 56 °
Overload recovery time VIN  × gain > VS 300 ns
THD+N Total harmonic distortion + noise VS = 40 V, VO = 6 VRMS, G = +1, f = 1 kHz 0.00012 %
EMIRR EMI rejection ratio f = 1 GHz 53 dB
OUTPUT
  Voltage output swing from rail Positive rail headroom VS = 40 V, RL = 10 kΩ   115 210 mV
VS = 40 V, RL = 2 kΩ   520 965
Negative rail headroom VS = 40 V, RL = 10 kΩ   105 215
VS = 40 V, RL = 2 kΩ   500 1030
ISC Short-circuit current ±26 mA
CLOAD Capacitive load drive 300
 pF
ZO Open-loop output impedance f = 1 MHz, IO = 0 A 125 Ω
POWER SUPPLY
IQ Quiescent current per amplifier IO = 0 A 937.5 1125 µA
IO = 0 A, (TL071H) 960 1156
IO = 0 A TA = –40°C to +125°C 1130
IO = 0 A, (TL072H) 1143
IO = 0 A, (TL071H) 1160
Turn-on time At TA = 25°C, VS = 40 V, VS ramp rate > 0.3 V/µs 60 μs
(1) Maximum IB and IOS data are specified based on characterization results.