SLVSIM2A June   2025  – August 2025 TPD4S480-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings—JEDEC Specification
    3. 5.3 ESD Ratings—IEC Specification
    4. 5.4 ESD Ratings—ISO Specification
    5. 5.5 Recommended Operating Conditions
    6. 5.6 Thermal Information
    7. 5.7 Electrical Characteristics
    8. 5.8 Timing Requirements
    9. 5.9 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 4-Channels of Short-to-VBUS Overvoltage Protection (CC1, CC2, SBU1, SBU2 Pins or CC1, CC2, DP, DM Pins): 63VDC Tolerant
      2. 6.3.2 4-Channels of IEC 61000-4-2 ESD Protection (CC1, CC2, SBU1, SBU2 Pins)
      3. 6.3.3 CC1, CC2 Overvoltage Protection FETs 600-mA Capable for Passing VCONN Power
      4. 6.3.4 CC Dead Battery Resistors Integrated for Handling the Dead Battery Use Case in Mobile Devices
      5. 6.3.5 EPR Adapter
        1. 6.3.5.1 VBUS Divider
        2. 6.3.5.2 EPR Blocking FET Gate Driver
    4. 6.4 Device Functional Modes
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
    3. 7.3 Design Requirements
      1. 7.3.1 EPR Design Requirements
    4. 7.4 Detailed Design Procedure
      1. 7.4.1 VBIAS Capacitor Selection
      2. 7.4.2 CC Line Capacitance
      3. 7.4.3 FLT Pin Operation
      4. 7.4.4 Dead Battery Operation
    5. 7.5 Application Curves
    6. 7.6 Power Supply Recommendations
    7. 7.7 Layout
      1. 7.7.1 Layout Guidelines
      2. 7.7.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Documentation Support
      1. 8.1.1 Related Documentation
    2. 8.2 Receiving Notification of Documentation Updates
    3. 8.3 Support Resources
    4. 8.4 Trademarks
    5. 8.5 Electrostatic Discharge Caution
    6. 8.6 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.3.1 4-Channels of Short-to-VBUS Overvoltage Protection (CC1, CC2, SBU1, SBU2 Pins or CC1, CC2, DP, DM Pins): 63VDC Tolerant

The TPD4S480-Q1 provides 4-channels of short-to-VBUS Overvoltage Protection for the CC1, CC2, SBU1, and SBU2 pins (or the CC1, CC2, DP, and DM pins) of the USB Type-C connector. The TPD4S480-Q1 is able to handle 63VDC on its C_CC1, C_CC2, C_SBU1, and C_SBU2 pins. This level of protection is necessary because according to the USB PD specification, with VBUS set for 48-V operation, the VBUS voltage is allowed to legally swing up to 50.4V and 50.9V on voltage transitions from a different USB PD VBUS voltage. To support possible ringing during a short event, the TPD4S480-Q1 builds in tolerance up to 63VBUS to provide margin above this 50.9V specification.

When a short-to-VBUS event occurs, ringing happens due to the RLC elements in the hot-plug event. Ringing up to twice the settling voltage appears on the connector if the resistance is low in the RLC circuit. Ringing of more than twice the DC level is generated if any capacitor on the line derates in capacitance value during the short-to-VBUS event. This behavior means that more than 90V is seen on a USB Type-C pin during a short-to-VBUS event. The TPD4S480-Q1 has built in circuit protection to handle this ringing. The diode clamps used for IEC ESD protection also clamp the ringing voltage during the short-to-VBUS event to limit the peak ringing to approximately 53V. Additionally, the overvoltage protection FETs integrated inside the TPD4S480-Q1 are 63V tolerant, therefore being capable of supporting the high-voltage ringing waveform that is experienced during the short-to-VBUS event. The TPD4S480-Q1 handles short-to-VBUS hot-plug events with hot-plug voltages as high as 51VDC because of the well-designed combination of voltage clamps and 63V tolerant OVP FETs.

The TPD4S480-Q1 has an extremely fast turnoff time of 70ns typical. Furthermore, additional voltage clamps are placed after the OVP FET on the system side (CC1, CC2, SBU1, SBU2) pins of the TPD4S480-Q1, to further limit the voltage and current that are exposed to the USB Type-C CC/PD controller during the 70ns interval while the OVP FET is turning off. The combination of connector side voltage clamps, OVP FETs with extremely fast turnoff time, and system side voltage clamps all work together to enable the level of stress seen on a CC1, CC2, SBU1, or SBU2 pin during a short-to-VBUS event to be less than or equal to an HBM event.

The SBU OVP FETs are designed to be able to optionally protect the DP, DM (USB2.0) pins in lieu of the SBU pins. Some systems designers also prefer to protect the DP, DM pins from short-to-VBUS events due to the potential for moisture/water in the connector to short the VBUS pins to DP, DM pins. This protection is applicable in cases where the end equipment with a USB Type-C connector is trying to be made water-proof. If desiring to protect the DP, DM pins on the USB Type-C connector from a short-to-VBUS event, connect the C_SBUx pins to the DP, DM pins on the USB Type-C connector, and the SBUx pins to the USB2.0 pins of the system device being protected from the short-to-VBUS event.