SLVSIM2A June   2025  – August 2025 TPD4S480-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings—JEDEC Specification
    3. 5.3 ESD Ratings—IEC Specification
    4. 5.4 ESD Ratings—ISO Specification
    5. 5.5 Recommended Operating Conditions
    6. 5.6 Thermal Information
    7. 5.7 Electrical Characteristics
    8. 5.8 Timing Requirements
    9. 5.9 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 4-Channels of Short-to-VBUS Overvoltage Protection (CC1, CC2, SBU1, SBU2 Pins or CC1, CC2, DP, DM Pins): 63VDC Tolerant
      2. 6.3.2 4-Channels of IEC 61000-4-2 ESD Protection (CC1, CC2, SBU1, SBU2 Pins)
      3. 6.3.3 CC1, CC2 Overvoltage Protection FETs 600-mA Capable for Passing VCONN Power
      4. 6.3.4 CC Dead Battery Resistors Integrated for Handling the Dead Battery Use Case in Mobile Devices
      5. 6.3.5 EPR Adapter
        1. 6.3.5.1 VBUS Divider
        2. 6.3.5.2 EPR Blocking FET Gate Driver
    4. 6.4 Device Functional Modes
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
    3. 7.3 Design Requirements
      1. 7.3.1 EPR Design Requirements
    4. 7.4 Detailed Design Procedure
      1. 7.4.1 VBIAS Capacitor Selection
      2. 7.4.2 CC Line Capacitance
      3. 7.4.3 FLT Pin Operation
      4. 7.4.4 Dead Battery Operation
    5. 7.5 Application Curves
    6. 7.6 Power Supply Recommendations
    7. 7.7 Layout
      1. 7.7.1 Layout Guidelines
      2. 7.7.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Documentation Support
      1. 8.1.1 Related Documentation
    2. 8.2 Receiving Notification of Documentation Updates
    3. 8.3 Support Resources
    4. 8.4 Trademarks
    5. 8.5 Electrostatic Discharge Caution
    6. 8.6 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5.7 Electrical Characteristics

over operating junction temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
CC OVP Switches
RON On Resistance of CC OVP FETs CCx = 5.5V, TJ ≤ 85 ℃ 272 420 mΩ
CON_CC Equivalent on Capacitance Capacitance from CCx or C_CCx to GND when device is powered. Measure at VC_CCx/VCCx = 0V to 1.2V, f = 400kHz. 40 74 120 pF
RD_DB Dead Battery Pull-Down Resistors (only present when device is unpowered) VC_CCx = 2.6V 4.1 5.1 6.1 kΩ
VTH_DB Threshold voltage of the pull-down FET in series with RD during dead battery IC_CCx = 80μA 0.5 0.9 1.2 V
VOVPCC OVP Threshold on CC Pins Place 5.5V on C_CCx. Step up C_CCx until FLT pin is asserted. Put 100mA load through the CC FET and see the FET shuts off. 5.6 5.9 6.2 V
VOVPCC_HYS Hysteresis on CC OVP Place 6.5 V on C_CCx. Step down the
voltage on C_CCx until the FLT pin is
deasserted. Measure difference
between rising and falling OVP
threshold for C_CCx. 		50 mV
BWON On Bandwidth Single Ended (-3dB) Measure the -3 dB bandwidth from
C_CCx to CCx. Single ended
measurement, 50-Ω system. Vcm = 0.1V to 1.2 V. 		125 MHz
VSTBUS_CC Short-to-VBUS tolerance on the CC pins Hot-Plug C_CCx with a 1 meter USB
Type C Cable, place a 30-Ω load on
CCx		 51 V
VSTBUS_CC_CLAMP Short-to-VBUS System-Side Clamping Voltage on the CC pins (CCx) Hot-Plug C_CCx with a 1 meter USB
Type C Cable. Hot-Plug voltage
C_CCx = 51 V. VPWR = 3.3 V. Place
a 30-Ω load on CCx. 		7 V
SBU OVP Switches
RON On Resistance of SBU OVP FETs SBUx = 3.6 V. –40°C ≤ TJ ≤ +85°C 4 6.8 Ω
CON_SBU Equivalent on Capacitance Capacitance from SBUx or C_SBUx to GND when device is powered. Measure at VC_SBUx/VSBUx = 0.3V to 4.0V. 6 pF
VOVPSBU OVP Threshold on SBU Pins Place 3.6V on C_SBUx. Step up C_SBUx until FLT pin is asserted. 4.0 4.2 4.41 V
VOVPSBU_HYS Hysteresis on SBU OVP Place 5 V on C_CCx. Step down the
voltage on C_CCx until the FLT pin is
deasserted. Measure difference
between rising and falling OVP
threshold for C_SBUx. 		50 mV
BWON On Bandwidth Single Ended (-3dB) Measure the -3 dB bandwidth from C_SBUx to SBUx. Single ended measurement, 50Ω system. Vcm = 0.1V to 3.6V. 600 760 MHz
XTALK Crosstalk Measure crosstalk at f = 1 MHz from SBU1 to C_SBU2 or SBU2 to C_SBU1. Vcm1 = 3.6 V, Vcm2 = 0.3 V. Terminate open sides to 50Ω. -70 dB
VSTBUS_SBU Short-to-VBUS tolerance on the SBU pins Hot-Plug C_SBUx with a 1 meter USB
Type C Cable. Put a 100-nF capacitor
in series with a 40-Ω resistor to GND
on SBUx.		 51 V
VSTBUS_SBU_CLAMP Short-to-VBUS System-Side Clamping Voltage on the SBU pins (SBUx) Hot-Plug C_SBUx with a 1 meter USB Type C Cable. Hot-Plug voltage C_SBUx = 51V. VPWR = 3.3 V. Put a 150-nF capacitor in series with a 40-Ω resistor to GND on SBUx. 7 V
EPR Adapter
VBUS_DIV_SPR VBUS_LV to VBUS divider ratio, SPR Mode VBUS_LV/VBUS, EPR_EN = 0, VBUS = 4.5 - 21V, I_VBUS_LV = 0-20mA 1 V/V
VBUS_DIV_EPR VBUS_LV to VBUS divider ratio, EPR Mode VBUS_LV/VBUS, EPR_EN = 1, VBUS = 26.6-50.4, I_VBUS_LV = 0-20mA 0.42 V/V
I_VBUSLV Current from VBUS_LV 20 mA
VFWD_VBUSLV VBUS to VBUS_LV forward voltage drop I_VBUS_LV=20mA, VBUS=4.5V, EPR_EN=0 700 mV
VFWD_VBUSLV VBUS to VBUS_LV forward voltage drop I_VBUS_LV=20mA, VBUS=26V, EPR_EN=1 2000 mV
EPR_THRESH_R Automatic EPR threshold rising VBUS threshold 22.7 24 V
EPR_THRESH_F Automatic EPR threshold falling VBUS threshold 22.4 23.4 V
V_EPR_BLK_G Gate Drive voltage for EPR_BLK_G 0 ≤ VBUS ≤ 22 V 5 12 V
I_EPR_BLK_G Gate Driver Sourcing Current 0 ≤ VEPR_BLKG-VVBUS ≤ 5 V, 0 V ≤ VVBUS ≤ 22 V, measure IEPR_BLK_G 4 µA
EPR_EN_V+ EPR_EN rising threshold 0.7*VPWR V
EPR_EN_V- EPR_EN falling threshold 0.3*VPWR V
Power Supply and Leakage Currents
VPWR_UVLO VPWR Undervoltage Lockout Place 1 V on VPWR and raise voltage until SBU or CC FETs turn-on. 2.1 2.3 2.6 V
VPWR_UVLO_HYS VPWR UVLO Hysteresis Place 3 V on VPWR and lower voltage
until SBU or CC FETs turnoff; measure
difference between rising and falling
UVLO to calculate hysteresis. 		70 100 130 mV
IVPWR VPWR supply current VPWR = 3.3 V (typical), VPWR = 4.5 V
(maximum). –40°C ≤ TJ ≤ +85°C. 		112 160 µA
IC_CC_LEAK Leakage current for C_CCx pins when device is powered VPWR = 3.3 V, VC_CCx = 3.6 V, CCx pins are floating, measure leakage current into C_CCx pins. 5 µA
IC_SBU_LEAK Leakage current for C_SBUx pins when device is powered VPWR = 3.3 V, VC_SBUx = 3.6 V, SBUx pins are floating, measure leakage current into C_SBUx pins. Result should be same if SBUx side is biased and C_SBUx is left floating.-40°C ≤ TJ ≤ +85°C 3.2 µA
IC_CC_LEAK_OVP Leakage current for C_CCx pins when device is in OVP VPWR = 0 V or 3.3 V, VC_CCx = 51 V, CCx pins are set to 0 V, measure leakage current into C_CCx pins. 1200 µA
IC_SBU_LEAK_OVP Leakage current for C_SBUx pins when device is in OVP VPWR = 0 V or 3.3 V, VC_SBUx = 51 V, SBUx pins are set to 0 V, measure leakage current into C_SBUx pins. 720 µA
ICC_LEAK_OVP Leakage current for CC pins when device is in OVP VPWR = 0 V or 3.3 V, VC_CCx = 51 V, CCx pins are set to 0 V, measure leakage current out of CCx pins.  30 µA
ISBU_LEAK_OVP Leakage current for SBU pins when device is in OVP VPWR = 0 V, VC_SBUx = 51 V, SBUx pins are set to 0 V, measure leakage current into SBUx pins.  -1 1 µA
/FLT Pin
VOL Low-level output voltage IOL = 3mA. Measure voltage at FLT pin. 0.4 V
Over Temperature Protection
TSD_RISING The rising over-temperature protection shutdown threshold 150 175 °C
TSD_FALLING The falling over-temperature protection shutdown threshold 130 140 °C
TSD_HYST The over-temperature protection shutdown threshold hysteresis 35 °C