SLVSET9G September   2018  – April 2026 TPS1663

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  8. 7 Parameter Measurement Information
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Hot Plug-In and In-Rush Current Control
        1. 8.3.1.1 Thermal Regulation Loop
      2. 8.3.2  Undervoltage Lockout (UVLO)
      3. 8.3.3  Overvoltage Protection (OVP)
      4. 8.3.4  Overload and Short Circuit Protection
        1. 8.3.4.1 Overload Protection
        2. 8.3.4.2 Short Circuit Protection
          1. 8.3.4.2.1 Start-Up With Short-Circuit On Output
      5. 8.3.5  Output Power Limiting, PLIM (TPS16632 and TPS16637)
      6. 8.3.6  Current Monitoring Output (IMON)
      7. 8.3.7  FAULT Response (FLT)
      8. 8.3.8  Power Good Output (PGOOD)
      9. 8.3.9  IN, P_IN, OUT and GND Pins
      10. 8.3.10 Thermal Shutdown
      11. 8.3.11 Low Current Shutdown Control (SHDN)
    4. 8.4 Device Functional Modes
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Programming the Current-Limit Threshold R(ILIM) Selection
        2. 9.2.2.2 Undervoltage Lockout and Overvoltage Set Point
        3. 9.2.2.3 Setting Output Voltage Ramp Time (tdVdT)
          1. 9.2.2.3.1 Support Component Selections RPGOOD and C(IN)
      3. 9.2.3 Application Curves
    3. 9.3 System Examples
      1. 9.3.1 Simple 24V Power Supply Path Protection
    4. 9.4 Power Supply Recommendations
      1. 9.4.1 Transient Protection
    5. 9.5 Layout
      1. 9.5.1 Layout Guidelines
      2. 9.5.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.6 Timing Requirements

–40°C ≤ TA = TJ ≤ +125°C, 4.5V < V(IN) = V(P_IN) < 60V, V(SHDN) = 2V, R(ILIM) = 30kΩ, IMON = PGOOD = FLT = OPEN, C(OUT) = 1μF, C(dVdT) = OPEN. (All voltages referenced to GND, (unless otherwise noted))
PARAMETER TEST CONDITIONS MIN NOM MAX UNIT
UVLO INPUT (UVLO)
UVLO_ton(dly) UVLO switch turnon delay UVLO↑ (100mV above V(UVLOR)) to V(OUT) = 100mV , C(dVdT) ≥ 10nF,  [C(dVdT) in nF] 742 + 49.5x C(dVdT) µs
UVLO_toff(dly) UVLO switch turnoff delay UVLO↓(20mV below V(UVLOF)) to FLT↓ 9 11 16 µs
tUVLO_FLT(dly) UVLO to Fault de-assertion delay UVLO↑  to FLT ↑ delay 500 617 700 µs
OVER VOLTAGE PROTECTION INPUT (OVP)
OVP_toff(dly) OVP switch turnOFF delay OVP↑ (20mV above V(OVPR)) to FLT↓ 8.5 11 14 µs
OVP_ton(dly) OVP switch disable delay OVP↓ (100mV below V(OVPF)) to FET ON ,  C(dVdT) ≥ 10nF,  [C(dVdT) in nF] 150 + 49.5x C(dVdT) µs
tOVC(dly) Maximum duration in over voltage clamp operation TPS16632 Only 162 ms
OVC_tFLT(dly) FLT assertion delay in over voltage clamp operation TPS16632 Only 617 µs
SHUTDOWN CONTROL INPUT (SHDN)
tSD(dly) SHUTDOWN entry delay SHDN↓ (below V(SHUTF)) to FET OFF 0.8 1 1.5 µs
CURRENT LIMIT
tFASTTRIP(dly) Hot-short response time I(OUT) > I(SCP) 1 µs
Soft short response I(FASTTRIP) < I(OUT) < I(SCP) 2.2 3.2 4.5 µs
tCL_PLIM(dly) Maximum duration in current & (power limiting: TPS16632 and TPS16637) 129 162 202 ms
tCL_PLIM_FLT(dly) FLT delay in current & (power limiting: TPS16632 and TPS16637) 1.09 1.3 1.6 ms
OUTPUT RAMP CONTROL (dVdT)
t(FASTCHARGE) Output ramp time in fast charging C(dVdT) = Open, 10% to 90% V(OUT), C(OUT) = 1 µF; V(IN) = 24V 350 495 700 µs
t(dVdT) Output ramp time C(dVdT) = 22nF, 10% to 90% V(OUT), V(IN) = 24V 8.35 ms
POWER GOOD (PGOOD)
tPGOODR PGOOD delay (deglitch) time Rising edge 8 11.5 13 ms
tPGOODF PGOOD delay (deglitch) time Falling edge 8 10 13 ms
THERMAL PROTECTION
t(TSD_retry) Retry delay in TSD MODE = GND 500 648 800 ms
t(Treg_timeout) Thermal Regulation Timeout 1.1 1.25 1.5 s