SNVSBF6B October   2019  – December 2020 TPSM265R1

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics
    6. 6.6  Typical Characteristics (VIN = 5 V)
    7. 6.7  Typical Characteristics (VIN = 12 V)
    8. 6.8  Typical Characteristics (VIN = 24 V)
    9. 6.9  Typical Characteristics (VIN = 48 V)
    10. 6.10 Typical Characteristics (VIN = 65 V)
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Adjustable Output Voltage (FB)
      2. 7.3.2 Input Capacitor Selection
      3. 7.3.3 Output Capacitor Selection
      4. 7.3.4 Precision Enable (EN), Undervoltage Lockout (UVLO), and Hysteresis (HYS)
      5. 7.3.5 PFM Operation
      6. 7.3.6 Power Good (PGOOD)
      7. 7.3.7 Configurable Soft Start (SS)
        1. 7.3.7.1 Prebiased Start-up
      8. 7.3.8 Overcurrent Protection (OCP)
      9. 7.3.9 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 Shutdown Mode
      2. 7.4.2 Standby Mode
      3. 7.4.3 Active Mode
      4. 7.4.4 Sleep Mode
  8. 8 Applications and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Custom Design With WEBENCH® Tools
        2. 8.2.2.2 Output Voltage Setpoint
        3. 8.2.2.3 Input Capacitors
        4. 8.2.2.4 Output Capacitor Selection
        5. 8.2.2.5 UVLO Programming
        6. 8.2.2.6 Soft-Start Capacitor – CSS
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
      1. 10.2.1 Theta JA versus PCB Area
      2. 10.2.2 Package Specifications
      3. 10.2.3 EMI
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
      2. 11.1.2 Development Support
      3. 11.1.3 Custom Design With WEBENCH® Tools
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Support Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.3.5 PFM Operation

The TPSM265R1 operates in Pulse Frequency Modulation (PFM) mode. The TPSM265R1 behaves as a hysteretic voltage regulator operating within upper and lower feedback regulation thresholds with typical 10 mV of hysteresis. Figure 7-4 is a representation of the relevant voltage waveforms and inductor current waveform. The TPSM265R1 provides the required switching pulses to recharge the output capacitance, followed by a sleep period where most of the internal circuits are shut off. The load current is supported by the output capacitor during this time, and the TPSM265R1 current consumption approaches the sleep quiescent current of 10.5 μA (typ). The sleep period duration depends on load current and output capacitance.

GUID-2BAAEC56-505C-4142-B5F8-CC29F05B55FE-low.gifFigure 7-4 PFM Mode SW Node Voltage, Feedback Voltage, and Inductor Current Waveforms