SLUSD12A October 2017 – February 2018 UCC28780
The switching pattern in AAM forces PWML and PWMH to alternate in a complementary fashion with dead-time in between, as shown in Figure 24. As the load current reduces, the negative magnetizing current (IM-) stays the same, while the positive magnetizing current (IM+) reduces by the internal peak current loop to regulate the output voltage. IM+ generates a current-feedback signal (VCS) on CS pin through a current-sense resistor (RCS) in series with QL, and a peak current threshold (VCST) in the current loop controls the peak current variation. Due to the nature of transition-mode (TM) operation, lowering the peak current with lighter load conditions results in higher switching frequency. When the load current increases to an over-power condition (IO(OPP)) where VCST correspondingly reaches an OPP threshold (VCST(OPP)) of the peak current loop, the OPP fault response will be triggered after a 160-ms timeout. The RUN signal stays high in AAM, so the half-bridge driver remains active.