SLUSD12A October   2017  – February 2018 UCC28780


  1. Features
  2. Applications
  3. Description
    1.     Device Images
      1.      Simplified Schematic
      2.      45-W, 20-V GaN-ACF Adapter Efficiency
  4. Revision History
  5. Pin Configuration and Functions
    1.     Pin Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information of SOIC
    5. 6.5 Thermal Information of WQFN
    6. 6.6 Electrical Characteristics
    7. 6.7 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Detailed Pin Description
      1. 7.3.1 BUR Pin (Programmable Burst Mode)
      2. 7.3.2 FB Pin (Feedback Pin)
      3. 7.3.3 VDD Pin (Device Bias Supply)
      4. 7.3.4 REF Pin (Internal 5-V Bias)
      5. 7.3.5 HVG and SWS Pins
      6. 7.3.6 RTZ Pin (Sets Delay for Transition Time to Zero)
      7. 7.3.7 RDM Pin (Sets Synthesized Demagnetization Time for ZVS Tuning)
      8. 7.3.8 RUN Pin (Driver Enable Pin)
      9. 7.3.9 SET Pin
    4. 7.4 Device Functional Modes
      1. 7.4.1  Adaptive ZVS Control with Auto-Tuning
      2. 7.4.2  Dead-Time Optimization
      3. 7.4.3  Control Law across Entire Load Range
      4. 7.4.4  Adaptive Amplitude Modulation (AAM)
      5. 7.4.5  Adaptive Burst Mode (ABM)
      6. 7.4.6  Low Power Mode (LPM)
      7. 7.4.7  Standby Power Mode (SBP)
      8. 7.4.8  Startup Sequence
      9. 7.4.9  Survival Mode of VDD
      10. 7.4.10 System Fault Protections
        1. Brown-In and Brown-Out
        2. Output Over-Voltage Protection
        3. Over-Temperature Protection
        4. Programmable Over-Power Protection
        5. Peak Current Limit
        6. Output Short-Circuit Protection
        7. Over-Current Protection
        8. Thermal Shutdown
      11. 7.4.11 Pin Open/Short Protections
        1. Protections on CS pin Fault
        2. Protections on HVG pin Fault
        3. Protections on RDM and RTZ pin Faults
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application Circuit
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. Input Bulk Capacitance and Minimum Bulk Voltage
        2. Transformer Calculations
          1. Primary-to-Secondary Turns Ratio (NPS)
          2. Primary Magnetizing Inductance (LM)
          3. Primary Turns (NP)
          4. Secondary Turns (NS)
          5. Turns of Auxiliary Winding (NA)
          6. Winding and Magnetic Core Materials
        3. Clamp Capacitor Calculation
        4. Bleed-Resistor Calculation
        5. Output Filter Calculation
        6. Calculation of ZVS Sensing Network
        7. Calculation of Compensation Network
      3. 8.2.3 Application Curves
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 General Considerations
      2. 10.1.2 RDM and RTZ Pins
      3. 10.1.3 SWS Pin
      4. 10.1.4 VS Pin
      5. 10.1.5 BUR Pin
      6. 10.1.6 FB Pin
      7. 10.1.7 CS Pin
      8. 10.1.8 GND Pin
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • D|16
  • RTE|16
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Calculation of ZVS Sensing Network

There are four components in the application circuit to help the depletion MOSFET (QS) perform ZVS sensing safely, CSWS, RSWS, DSWS, and RHVG. Design considerations and selection guidelines for the values of these components are given here.

At the rising edge of the switch node, the fast dV/dt coupling through the drain-to-source capacitance of QS (COSS(Qs)) generates a charge current flowing into the capacitive loading of the QS source pin. The result is a voltage overshoot on both the SWS pin and across the gate-to-source of QS (VGS(Qs)). The SWS pin, with an absolute maximum voltage of 38 V, can handle higher voltage stress than VGS(Qs). Therefore, a capacitor between the SWS pin and GND (CSWS) should be selected properly to prevent the voltage overshoot from damaging the QS gate. Since COSS(Qs) and CSWS form a voltage divider, the minimum CSWS (CSWS(MIN)) can be derived as

Equation 42. UCC28780 EquCswsmin.gif

where VGS_MAX(Qs) is the de-rated maximum gate-to-source voltage of QS, VHVG is the steady-state voltage level of 11 V, and CDsws is the parasitic capacitance of TVS diode (DSWS) on the SWS pin.

Without resistive damping, both the charge current on the rising edge of VSW and the discharge current on the falling edge of VSW are oscillatory with the parasitic inductance within the ZVS sensing network resonating with CSWS. Therefore, a series resistor (RSWS) between SWS pin and source-pin of QS is used to dampen the high-frequency ringing, helping to obtain a cleaner sensing signal on the SWS pin and preventing any high-frequency current from interfering with other noise-sensitive signals. RSWS can be expressed as:

Equation 43. UCC28780 Equ-Rswmin.gif

where LSWS is the lumped parasitic inductance including the packaging of QS and PCB traces of QS and CSWS return path.

Based on the above design guide, even though RSWS and CSWS may be sufficient to manage the voltage overshoot in normal operation, a low-capacitance TVS diode (DSWS) is still highly recommended to serve as a safety backup of the ZVS sensing network. A regular Zener diode is not suitable due to its high capacitance and slow clamping response.

Based on the above equations, a general recommendation is that a 50 V C0G-type ceramic capacitor of 22 pF for CSWS, a chip resistor no higher than 120 Ω for RSWS, and a TVS diode with the clamp voltage between 18 V to 24 V for DSWS. Too large of RSWS or CSWS introduces a sensing delay between VSW and SWS pin, so the ZVS control pulls down VSW earlier than expected before the end of tZ by unnecessarily extending tDM. The recommended RSWS and CSWS values only introduce a minor 2.6-ns delay, so the ZVS control is not be affected.

Another issue with too large of RSWS is that an additional voltage drop may be created by the charge current through COSS(Qs) during high dV/dt events of VSW, which becomes another voltage stress onto the gate-to-source voltage of QS . For the power stage that can generate very high dV/dt, lowering RSWS and increasing CSWS may be necessary to enhance the protection on QS. Alternatively, a back-to-back TVS can be added between the gate and source pins of QS to provide a direct clamping to the possible over-voltage stress condition. Furthermore, a high-impedance discharge resistor (RHVG) between the gate and source pins of QS helps to discharge the residual voltage on the gate capacitance, and RHVG around 1 MΩ should be enough to serve the purpose. Note that too small RHVG can hurt standby power, since it creates a continuous current flowing through QS.