SLUSD12A October   2017  – February 2018 UCC28780


  1. Features
  2. Applications
  3. Description
    1.     Device Images
      1.      Simplified Schematic
      2.      45-W, 20-V GaN-ACF Adapter Efficiency
  4. Revision History
  5. Pin Configuration and Functions
    1.     Pin Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information of SOIC
    5. 6.5 Thermal Information of WQFN
    6. 6.6 Electrical Characteristics
    7. 6.7 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Detailed Pin Description
      1. 7.3.1 BUR Pin (Programmable Burst Mode)
      2. 7.3.2 FB Pin (Feedback Pin)
      3. 7.3.3 VDD Pin (Device Bias Supply)
      4. 7.3.4 REF Pin (Internal 5-V Bias)
      5. 7.3.5 HVG and SWS Pins
      6. 7.3.6 RTZ Pin (Sets Delay for Transition Time to Zero)
      7. 7.3.7 RDM Pin (Sets Synthesized Demagnetization Time for ZVS Tuning)
      8. 7.3.8 RUN Pin (Driver Enable Pin)
      9. 7.3.9 SET Pin
    4. 7.4 Device Functional Modes
      1. 7.4.1  Adaptive ZVS Control with Auto-Tuning
      2. 7.4.2  Dead-Time Optimization
      3. 7.4.3  Control Law across Entire Load Range
      4. 7.4.4  Adaptive Amplitude Modulation (AAM)
      5. 7.4.5  Adaptive Burst Mode (ABM)
      6. 7.4.6  Low Power Mode (LPM)
      7. 7.4.7  Standby Power Mode (SBP)
      8. 7.4.8  Startup Sequence
      9. 7.4.9  Survival Mode of VDD
      10. 7.4.10 System Fault Protections
        1. Brown-In and Brown-Out
        2. Output Over-Voltage Protection
        3. Over-Temperature Protection
        4. Programmable Over-Power Protection
        5. Peak Current Limit
        6. Output Short-Circuit Protection
        7. Over-Current Protection
        8. Thermal Shutdown
      11. 7.4.11 Pin Open/Short Protections
        1. Protections on CS pin Fault
        2. Protections on HVG pin Fault
        3. Protections on RDM and RTZ pin Faults
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application Circuit
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. Input Bulk Capacitance and Minimum Bulk Voltage
        2. Transformer Calculations
          1. Primary-to-Secondary Turns Ratio (NPS)
          2. Primary Magnetizing Inductance (LM)
          3. Primary Turns (NP)
          4. Secondary Turns (NS)
          5. Turns of Auxiliary Winding (NA)
          6. Winding and Magnetic Core Materials
        3. Clamp Capacitor Calculation
        4. Bleed-Resistor Calculation
        5. Output Filter Calculation
        6. Calculation of ZVS Sensing Network
        7. Calculation of Compensation Network
      3. 8.2.3 Application Curves
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 General Considerations
      2. 10.1.2 RDM and RTZ Pins
      3. 10.1.3 SWS Pin
      4. 10.1.4 VS Pin
      5. 10.1.5 BUR Pin
      6. 10.1.6 FB Pin
      7. 10.1.7 CS Pin
      8. 10.1.8 GND Pin
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • D|16
  • RTE|16
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Pin Configuration and Functions

D Package
16-Pin SOIC
Top View
UCC28780 soic_slusd12.gif
RTE Package
16-Pin WQFN
Top View
UCC28780 vqfn_slusd12.gif

Pin Functions

BUR 15 13 I This pin is used to program the burst level of the converter at light load. A resistive divider between REF and GND is used to set a voltage at this pin to determine the peak current level when the converter enters the adaptive burst mode. In addition, the Thevenin resistance on BUR pin (equivalent resistance of the divider resistors in parallel) is used to set an offset voltage for smooth mode transition which increases the peak current level when the converter enters the low power mode.
CS 3 1 I This is the current sense input pin. This pin couples through a line-compensation resistor to a current-sense resistor to sense and control the peak primary current in each switching cycle. A current sourced from this pin, which magnitude is proportional to the converter’s input voltage derived from the VS-pin input signal, creates an offset voltage across the line-compensation resistor to program an OPP level at high line.
FB 12 10 I The feedback current signal to close the converter’s regulation loop is coupled to this pin. This pin presents a 4-V output that is designed to have 0-µA to 75-µA current pulled out of the pin corresponding to the converter operating from full-power to zero-power conditions.
GND 2 16 G Ground reference and return for all controller signals.
HVG 8 6 O The high-voltage gate pin is used to control the gate of an external depletion-mode MOSFET for start-up and switch-node voltage sensing. A 2.2-nF ceramic bypass capacitor to ground is required.
NTC 11 9 I This is an interface to an external NTC (negative temperature coefficient) thermistor for remote temperature sensing. Pulling this pin low shuts down PWM action and initiates a fault response.
PWMH 5 3 O The PWMH pin is a logic-level output signal used to control the gate of the high-side clamp switch through an external gate driver.
PWML 4 2 O The PWML pin is a logic-level output signal used to control the gate of the low-side primary switch through an external gate driver.
RDM 14 12 I A resistor to ground on this pin programs a synthesized demagnetization time used to control the on-time of the high-side switch to achieve zero voltage switching on the low-side switch. The controller applies a voltage on this pin that varies with the output voltage derived from the VS pin signal.
REF 16 14 O 5V reference output that requires a 0.1-µF ceramic bypass capacitor to ground. This reference is used to power internal circuits and can supply a limited external load current.
RTZ 13 11 I A resistor to ground on this pin programs an adaptive transition-to-zero delay from the turn-off edge of the high-side clamp switch to the turn-on edge of the low-side switch.
RUN 6 4 O This output pin is high when the controller is in a run state. During start-up and wait states this output is low. It can be used to enable and disable the external gate drivers to reduce the static power consumption. There is a preset delay, tD(RUN-PWML), of about 2.2 µs that delays the initiation of PWML switching after this pin has gone high.
SET 10 8 I This pin is used to configure the controller to be optimized for Gallium Nitride (GaN) power FETs or silicon (Si) power FETs on the primary side. Depending on setting, it will optimize parameters of the ZVS control loop, dead-time adjustment, and protection features. When pulled high to REF pin, it is optimized for Si FETs. When pulled low to GND, it is optimized for GaN FETs .
SWS 7 5 I This sensing input is used to monitor the switch-node voltage as it nears zero volts in normal operation. During start-up, this pin is connected to the VDD pin internally to allow the high-voltage sensing network to provide start-up current.
VDD 1 15 P Bias power input to the controller. A hold-up capacitor to ground is required for the bias power supplied from the transformer auxiliary winding to this pin.
VS 9 7 I This voltage sensing input pin is coupled to the auxiliary winding of the converter’s transformer via a resistor divider. The pin and the associated external resistors are used to monitor the output and input voltages of the converter.
I = Input, O = Output, P = Power, G = Ground