SLUSD12A October   2017  – February 2018 UCC28780


  1. Features
  2. Applications
  3. Description
    1.     Device Images
      1.      Simplified Schematic
      2.      45-W, 20-V GaN-ACF Adapter Efficiency
  4. Revision History
  5. Pin Configuration and Functions
    1.     Pin Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information of SOIC
    5. 6.5 Thermal Information of WQFN
    6. 6.6 Electrical Characteristics
    7. 6.7 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Detailed Pin Description
      1. 7.3.1 BUR Pin (Programmable Burst Mode)
      2. 7.3.2 FB Pin (Feedback Pin)
      3. 7.3.3 VDD Pin (Device Bias Supply)
      4. 7.3.4 REF Pin (Internal 5-V Bias)
      5. 7.3.5 HVG and SWS Pins
      6. 7.3.6 RTZ Pin (Sets Delay for Transition Time to Zero)
      7. 7.3.7 RDM Pin (Sets Synthesized Demagnetization Time for ZVS Tuning)
      8. 7.3.8 RUN Pin (Driver Enable Pin)
      9. 7.3.9 SET Pin
    4. 7.4 Device Functional Modes
      1. 7.4.1  Adaptive ZVS Control with Auto-Tuning
      2. 7.4.2  Dead-Time Optimization
      3. 7.4.3  Control Law across Entire Load Range
      4. 7.4.4  Adaptive Amplitude Modulation (AAM)
      5. 7.4.5  Adaptive Burst Mode (ABM)
      6. 7.4.6  Low Power Mode (LPM)
      7. 7.4.7  Standby Power Mode (SBP)
      8. 7.4.8  Startup Sequence
      9. 7.4.9  Survival Mode of VDD
      10. 7.4.10 System Fault Protections
        1. Brown-In and Brown-Out
        2. Output Over-Voltage Protection
        3. Over-Temperature Protection
        4. Programmable Over-Power Protection
        5. Peak Current Limit
        6. Output Short-Circuit Protection
        7. Over-Current Protection
        8. Thermal Shutdown
      11. 7.4.11 Pin Open/Short Protections
        1. Protections on CS pin Fault
        2. Protections on HVG pin Fault
        3. Protections on RDM and RTZ pin Faults
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application Circuit
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. Input Bulk Capacitance and Minimum Bulk Voltage
        2. Transformer Calculations
          1. Primary-to-Secondary Turns Ratio (NPS)
          2. Primary Magnetizing Inductance (LM)
          3. Primary Turns (NP)
          4. Secondary Turns (NS)
          5. Turns of Auxiliary Winding (NA)
          6. Winding and Magnetic Core Materials
        3. Clamp Capacitor Calculation
        4. Bleed-Resistor Calculation
        5. Output Filter Calculation
        6. Calculation of ZVS Sensing Network
        7. Calculation of Compensation Network
      3. 8.2.3 Application Curves
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 General Considerations
      2. 10.1.2 RDM and RTZ Pins
      3. 10.1.3 SWS Pin
      4. 10.1.4 VS Pin
      5. 10.1.5 BUR Pin
      6. 10.1.6 FB Pin
      7. 10.1.7 CS Pin
      8. 10.1.8 GND Pin
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • D|16
  • RTE|16
Thermal pad, mechanical data (Package|Pins)
Orderable Information

HVG and SWS Pins

The HVG pin provides a controlled voltage to the gate of the depletion-mode MOSFET (QS), enabling QS to serve both VVDD startup and lossless ZVS sensing from the high-voltage switch node (VSW). During VVDD startup, the UVLO circuit commands two power-path switches connecting SWS and HVG pins to VDD pin with two internal current-limit resistors (RDDS and RDDH) separately, as shown in Figure 16. In this configuration, QS behaves as a current source to charge the VDD capacitor (CVDD). RDDS is set at 12 kΩ when VVDD is below 1 V to limit the maximum fault current under VDD pin short events. RDDS is reduced to 1 kΩ when VVDD rises above 1 V to allow VVDD to charge faster. The maximum charge current (ISWS) is affected by RDDS, the external series resistance (RSWS) from SWS pin to QS, and the threshold voltage of QS (VTH(Qs)). ISWS can be calculated as

Equation 7. UCC28780 Equ-ISWS.gif
UCC28780 VDDstartup.gifFigure 16. Operation of the VDD Startup Circuit

After VVDD reaches VVDD(ON), the two power-path switches open the connections among SWS, HVG, and VDD pins. At this point, a third power-path switch connects an internal 11-V regulator to the HVG pin for configuring QS to perform lossless ZVS sensing. As QS gate is fixed at 11 V and the drain pin voltage of QS becomes higher than the sum of QS threshold voltage (VTH(Qs)) and the 11-V gate voltage, QS turns off and the source pin voltage of QS can no longer follow the drain pin voltage change, so this gate control method makes QS act as a high-voltage blocking device with the drain pin connected to VSW. When the controller is switching, VSW can be lower than 11 V, so QS turns on and forces the source pin voltage to follow VSW, becoming a replica of the VSW waveform at the lower voltage level, as illustrated in Figure 17.

The limited window for monitoring the VSW waveform suffices for ZVS control of the UCC28780, since the ZVS tuning threshold (VTH(SWS)) is lower than that, which is at 9 V for VSET = 5 V and at 4 V for VSET = 0 V. The 9-V threshold is the auto-tuning target of the internal adaptive ZVS control loop for realizing a partial ZVS condition on the ACF using Si primary switches. On the other hand, performing full ZVS operation is more suitable for the ACF with GaN primary switches. The 4-V threshold can help to better compensate sensing delay between VSW and the SWS pin more than using a 0-V threshold. The internal 11-V regulator requires a high quality ceramic bypass capacitor (CHVG) between the HVG pin and GND for noise filtering and providing compensation to the regulator circuitry. The minimum CHVG value is 2.2 nF and an X7R-type dielectric capacitor is recommended. The controller enters a fault state if the HVG pin is open or shorted to GND during VVDD start-up, or if VHVG overshoot is higher than VHVG(OV) of 13.8 V in run state. The output short current of HVG regulator (IS(HVG)) is self-limited to around 1mA.

UCC28780 ZVSsense.gifFigure 17. ZVS Sensing by Reusing the VDD Startup Circuit