SLUSDB2A August 2018 – December 2021 UCC28951
PRODUCTION DATA
Selecting FETs for a design is an iterative process. To meet the power requirements of this design, we select 75-V, 120-A FETs, from Fairchild, part number FDP032N08. These FETs have the following characteristics.
Calculate average FET C_{OSS} (C_{OSS_QE_AVG}) based on the data sheet parameters for C_{OSS} (C_{OSS_SPEC}), and drain to source voltage where C_{OSS_SPEC} was measured (V_{ds_spec}), and the maximum drain to source voltage in the design (V_{dsQE}) that will be applied to the FET in the application.
The voltage across FET QE and QF when they are of isf:
The voltage where FET C_{OSS} is specified and tested in the FET data sheet:
The specified output capacitance from FET data sheet is:
The average QE and QF C_{OSS} [2] is calculated using Equation 80:
The QE and QF RMS current are:
To estimate FET switching loss the V_{g} vs. Q_{g} curve from the FET data sheet needs to be studied. First the gate charge at the beginning of the miller plateau needs to be determined (QE_{MILLER_MIN}) and the gate charge at the end of the miller plateau (QE_{MILLER_MAX}) for the given V_{DS}.
The maximum gate charge at the end of the miller plateau is:
The minimum gate charge at the beginning of the miller plateau is:
The FETs in this design are driven with a UCC27324 Gate Driver IC, setup to drive 4-A (I_{P}) of gate drive current.
Estimated FET V_{ds} rise and fall time using Equation 85:
Estimate QE and QF FET Losses (P_{QE}) using Equation 86:
Recalculate the power budget using Equation 88.