SLUSDB2A August 2018 – December 2021 UCC28951
Selecting FETs for a design is an iterative process. To meet the power requirements of this design, we select 75-V, 120-A FETs, from Fairchild, part number FDP032N08. These FETs have the following characteristics.
Calculate average FET COSS (COSS_QE_AVG) based on the data sheet parameters for COSS (COSS_SPEC), and drain to source voltage where COSS_SPEC was measured (Vds_spec), and the maximum drain to source voltage in the design (VdsQE) that will be applied to the FET in the application.
The voltage across FET QE and QF when they are of isf:
The voltage where FET COSS is specified and tested in the FET data sheet:
The specified output capacitance from FET data sheet is:
The average QE and QF COSS  is calculated using Equation 80:
The QE and QF RMS current are:
To estimate FET switching loss the Vg vs. Qg curve from the FET data sheet needs to be studied. First the gate charge at the beginning of the miller plateau needs to be determined (QEMILLER_MIN) and the gate charge at the end of the miller plateau (QEMILLER_MAX) for the given VDS.
The maximum gate charge at the end of the miller plateau is:
The minimum gate charge at the beginning of the miller plateau is:
The FETs in this design are driven with a UCC27324 Gate Driver IC, setup to drive 4-A (IP) of gate drive current.
Estimated FET Vds rise and fall time using Equation 85:
Estimate QE and QF FET Losses (PQE) using Equation 86:
Recalculate the power budget using Equation 88.