SLUSDB2A August   2018  – December 2021 UCC28951


  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Dissipation Ratings
    8. 6.8 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Start-Up Protection Logic
      2. 7.3.2  Voltage Reference (VREF)
      3. 7.3.3  Error Amplifier (EA+, EA–, COMP)
      4. 7.3.4  Soft-Start and Enable (SS/EN)
      5. 7.3.5  Light-Load Power Saving Features
      6. 7.3.6  Adaptive Delay, (Delay Between OUTA and OUTB, OUTC and OUTD (DELAB, DELCD, ADEL))
      7. 7.3.7  Adaptive Delay (Delay Between OUTA and OUTF, OUTB and OUTE (DELEF, ADELEF)
      8. 7.3.8  Minimum Pulse (TMIN)
      9. 7.3.9  Burst Mode
      10. 7.3.10 Switching Frequency Setting
      11. 7.3.11 Slope Compensation (RSUM)
      12. 7.3.12 Dynamic SR ON/OFF Control (DCM Mode)
      13. 7.3.13 Current Sensing (CS)
      14. 7.3.14 Cycle-by-Cycle Current Limit Current Protection and Hiccup Mode
      15. 7.3.15 Synchronization (SYNC)
      16. 7.3.16 Outputs (OUTA, OUTB, OUTC, OUTD, OUTE, OUTF)
      17. 7.3.17 Supply Voltage (VDD)
      18. 7.3.18 Ground (GND)
    4. 7.4 Device Functional Modes
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1.  Power Loss Budget
        2.  Preliminary Transformer Calculations (T1)
        3.  QA, QB, QC, QD FET Selection
        4.  Selecting LS
        5.  Selecting Diodes DB and DC
        6.  Output Inductor Selection (LOUT)
        7.  Output Capacitance (COUT)
        8.  Select FETs QE and QF
        9.  Input Capacitance (CIN)
        10. Current Sense Network (CT, RCS, R7, DA)
          1. Voltage Loop Compensation Recommendation
      3. 8.2.3 Application Curves
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Development Support
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Community Resources
    5. 11.5 Trademarks

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Synchronization (SYNC)

The UCC28951 allows flexible configuration of converters operating in synchronized mode by connecting all SYNC pins together and by configuration of the controllers as leader and/or followers. The controller configured as leader (resistor between RT and VREF) provides synchronization pulses at the SYNC pin with the frequency equal to 2X the converter frequency FSW(nom) and 0.5 duty cycle. The controller configured as a follower (resistor between RT and GND and 825-kΩ resistor between SS_EN pin to GND) does not generate the synchronization pulses. The follower controller synchronizes its own clock to the falling edge of the synchronization signal thus operating 90° phase shifted versus the leader converter’s frequency FSW(nom).

The output inductor in a full bridge converter sees a switching frequency which is twice that seen by the transformer. In the case of the UCC28951 this means that the output inductor operates at 2 × FSW(nom). This means that the 90° phase shift between leader and follower controllers gives a 180° phase shift between the currents in the output inductors and hence maximum ripple cancellation. For more information about synchronizing more than two UCC28951 devices, see Synchronizing Three or More UCC28950 Phase-Shifted, Full-Bridge Controllers (SLUA609).

If the synchronization feature is not used then the SYNC pin may be left floating, but connecting the SYNC pin to GND through a 10-kΩ resistor will reduce noise pickup and switching frequency jitter.

  • If any converter is configured as a follower, the SYNC frequency must be greater than or equal to 1.8 times the converter frequency.
  • follower converter does not start until at least one synchronization pulse has been received.
  • If any or all converters are configured as followers, then each converter operates at its own frequency without synchronization after receiving at least one synchronization pulse. Thus, If there is an interruption of synchronization pulses at the follower converter, then the controller uses its own internal clock pulses to maintain operation based on the RT value that is connected to GND in the follower converter.
  • In leader mode, SYNC pulses start after SS pin passes its enable threshold which is 0.55 V.
  • follower starts generating SS/EN voltage even though synchronization pulses have not been received.
  • TI recommends that the SS on the leader controller starts before the SS on the follower controller; therefore SS/EN pin on leader converter must reach its enable threshold voltage before SS/EN on the follower converter starts for proper operation. On the same note, TI also recommends that the TMIN resistors on both leader and follower are set at the same value.
GUID-E168A6C3-F6C1-40B5-98C1-88D3448E550C-low.gifFigure 7-16 SYNC_OUT (leader Mode) Timing Diagram
GUID-F229BC3B-D572-4A9D-AA57-819CDEDBE03E-low.gifFigure 7-17 SYNC_IN (follower Mode) Timing Diagram