at TA = 25°C,
AVDD1 = 5V, AVSS = 0V, AVDD2 = 2.5V, IOVDD = 1.8V, fCLK = 4.096MHz,
VREFP = 2.5V, VREFN = 0V, PGA gain = 1, RS =
0Ω, VCM = 2.5V, and fDATA = 500SPS (unless otherwise
noted)
Figure 5-9 Shorted Input FFT
Figure 5-11 Shorted Input FFT 
Figure 5-13 Full-Scale Input FFT 
Figure 5-15 Dynamic Range vs PGA Gain
Figure 5-17 Offset Drift Distribution
Figure 5-19 Gain
Error Distribution
Figure 5-21 Gain
Drift Distribution
| AVDD1 = 3.3V, fIN = 31.25Hz, VIN
= –0.5dBFS |
Figure 5-23 THD vs PGA Gain
| fIN = 31.25Hz, VIN =
–0.5dBFS |
Figure 5-25 THD vs Source
Impedance
Figure 5-27 PGA Input Current vs Input
Voltage
Figure 5-29 Reference Input Current vs
Temperature
Figure 5-31 CMRR vs Common-Mode Input
Frequency
Figure 5-33 Power-Supply Current vs
Temperature
Figure 5-35 IOVDD Current vs Data
Rate
Figure 5-10 Shorted Input FFT 
Figure 5-12 Full-Scale Input FFT 
| AIN2: 31.25Hz, –0.5dBFS signal, AIN1: input shorted
measured channel |
Figure 5-14 Channel Crosstalk
Figure 5-16 Offset Error Distribution
Figure 5-18 Gain
Error Distribution
Figure 5-20 Gain
Drift Distribution
Figure 5-22 Gain
Match Distribution
|
fIN = 31.25Hz, VIN =
–0.5dBFS |
Figure 5-24 THD vs Input
Frequency
Figure 5-26 PGA Input Current Noise
Distribution
Figure 5-28 Buffer Input Current vs
Input Voltage
Figure 5-30 Reference Input Current
Distribution
Figure 5-32 Power-Supply Current
Distribution
Figure 5-34 PSRR vs Power-Supply
Frequency