DLPS206 May   2021 DLPC7540

PRODUCTION DATA  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Power Electrical Characteristics
    6. 6.6  Pin Electrical Characteristics
    7. 6.7  DMD HSSI Electrical Characteristics
    8. 6.8  DMD Low-Speed LVDS Electrical Characteristics
    9. 6.9  V-by-One Interface Electrical Characteristics
    10. 6.10 FPD-Link LVDS Electrical Characteristics
    11. 6.11 USB Electrical Characteristics
    12. 6.12 System Oscillator Timing Requirements
    13. 6.13 Power Supply and Reset Timing Requirements
    14. 6.14 DMD HSSI Timing Requirements
    15. 6.15 DMD Low-Speed LVDS Timing Requirements
    16. 6.16 V-by-One Interface General Timing Requirements
    17. 6.17 FPD-Link Interface General Timing Requirements
    18. 6.18 Source Frame Timing Requirements
    19. 6.19 Synchronous Serial Port Interface Timing Requirements
    20. 6.20 Master and Slave I2C Interface Timing Requirements
    21. 6.21 Programmable Output Clock Timing Requirements
    22. 6.22 JTAG Boundary Scan Interface Timing Requirements (Debug Only)
    23. 6.23 JTAG ARM Multi-Ice Interface Timing Requirements (Debug Only)
    24. 6.24 Multi-Trace ETM Interface Timing Requirements
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Input Sources
      2. 7.3.2 Processing Delays
      3. 7.3.3 FPD-Link Interface
      4. 7.3.4 V-by-One interface
      5. 7.3.5 DMD (HSSI) Interface
      6. 7.3.6 Program Memory Flash Interface
      7. 7.3.7 GPIO Supported Functionality
      8. 7.3.8 Debug Support
    4. 7.4 Device Operational Modes
      1. 7.4.1 Standby Mode
      2. 7.4.2 Active Mode
        1. 7.4.2.1 Normal Configuration
        2. 7.4.2.2 Low Latency Configuration
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
  9. Power Supply Recommendations
    1. 9.1 Power Supply Management
    2. 9.2 Hot Plug Usage
    3. 9.3 Power Supplies for Unused Input Source Interfaces
    4. 9.4 Power Supplies
      1. 9.4.1 1.15-V Power Supplies
      2. 9.4.2 1.21V Power Supply
      3. 9.4.3 1.8-V Power Supplies
      4. 9.4.4 3.3-V Power Supplies
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1  General Layout Guidelines
      2. 10.1.2  Power Supply Layout Guidelines
      3. 10.1.3  Layout Guidelines for Internal Controller PLL Power
      4. 10.1.4  Layout Guideline for DLPC7540 Reference Clock
        1. 10.1.4.1 Recommended Crystal Oscillator Configuration
      5. 10.1.5  V-by-One Interface Layout Considerations
      6. 10.1.6  FPD-Link Interface Layout Considerations
      7. 10.1.7  USB Interface Layout Considerations
      8. 10.1.8  DMD Interface Layout Considerations
      9. 10.1.9  General Handling Guidelines for Unused CMOS-Type Pins
      10. 10.1.10 Maximum Pin-to-Pin, PCB Interconnects Etch Lengths
    2. 10.2 Thermal Considerations
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
      2. 11.1.2 Device Nomenclature
        1. 11.1.2.1 Device Markings
        2. 11.1.2.2 Package Data
    2. 11.2 Trademarks
    3. 11.3 Electrostatic Discharge Caution
    4. 11.4 Glossary
      1. 11.4.1 Video Timing Parameter Definitions
  12. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Package Option Addendum

パッケージ・オプション

メカニカル・データ(パッケージ|ピン)
サーマルパッド・メカニカル・データ
発注情報

DMD (HSSI) Interface

The DLPC7540 Controller DMD interface supports two High Speed Serial Interface (HSSI) output-only interfaces for data transmission, a single low speed LVDS output-only interface for command write transactions, as well as a low speed single-ended input interface used for command read transactions. Each HSSI port supports full data-only inter-lane remapping within the port, but not between ports. When utilizing this feature, each unique data lane pair can only be mapped to one unique destination data lane pair, and Intra-lane remapping (i.e. swapping P with N) is not supported. In addition, the two HSSI ports can also be swapped. Lane and port remapping (specified in flash) can help with board layout as needed. The number of HSSI ports and number of HSSI lanes/per HSSI port required are based on DMD type and DMD display resolution. Table 7-18 shows some remapping examples. When both ports are used, they do not need to have the same pin mapping.

Table 7-18 Controller to DMD Pin Mapping Examples
DLPC7540 Controller PINS - REMAPPING EXAMPLES TO DMD PINSDMD PINS
BASELINEFLIP HSSI0 180
No FLIP HSSI1
SWAP HSSI0 PORT WITH HSSI1 PORTSWAP HSSI0 PORT WITH HSSI1 PORT AND MIXED REMAPPING
DMD_HSSI0_D0_P
DMD_HSSI0_D0_N
DMD_HSSI0_D7_P
DMD_HSSI0_D7_N
DMD_HSSI1_D0_P
DMD_HSSI1_D0_N
DMD_HSSI1_D2_P
DMD_HSSI1_D2_N
DMD_HSSI0_D0_P
DMD_HSSI0_D0_N
DMD_HSSI0_D1_P
DMD_HSSI0_D1_N
DMD_HSSI0_D6_P
DMD_HSSI0_D6_N
DMD_HSSI1_D1_P
DMD_HSSI1_D1_N
DMD_HSSI1_D3_P
DMD_HSSI1_D3_N
DMD_HSSI0_D1_P
DMD_HSSI0_D1_N
DMD_HSSI0_D2_P
DMD_HSSI0_D2_N
DMD_HSSI0_D5_P
DMD_HSSI0_D5_N
DMD_HSSI1_D2_P
DMD_HSSI1_D2_N
DMD_HSSI1_D0_P
DMD_HSSI1_D0_N
DMD_HSSI0_D2_P
DMD_HSSI0_D2_N
DMD_HSSI0_D3_P
DMD_HSSI0_D3_N
DMD_HSSI0_D4_P
DMD_HSSI0_D4_N
DMD_HSSI1_D3_P
DMD_HSSI1_D3_N
DMD_HSSI1_D1_P
DMD_HSSI1_D1_N
DMD_HSSI0_D3_P
DMD_HSSI0_D3_N
DMD_HSSI0_D4_P
DMD_HSSI0_D4_N
DMD_HSSI0_D3_P
DMD_HSSI0_D3_N
DMD_HSSI1_D4_P
DMD_HSSI1_D4_N
DMD_HSSI1_D6_P
DMD_HSSI1_D6_N
DMD_HSSI0_D4_P
DMD_HSSI0_D4_N
DMD_HSSI0_D5_P
DMD_HSSI0_D5_N
DMD_HSSI0_D2_P
DMD_HSSI0_D2_N
DMD_HSSI1_D5_P
DMD_HSSI1_D5_N
DMD_HSSI1_D7_P
DMD_HSSI1_D7_N
DMD_HSSI0_D5_P
DMD_HSSI0_D5_N
DMD_HSSI0_D6_P
DMD_HSSI0_D6_N
DMD_HSSI0_D1_P
DMD_HSSI0_D1_N
DMD_HSSI1_D6_P
DMD_HSSI1_D6_N
DMD_HSSI1_D4_P
DMD_HSSI1_D4_N
DMD_HSSI0_D6_P
DMD_HSSI0_D6_N
DMD_HSSI0_D7_P
DMD_HSSI0_D7_N
DMD_HSSI0_D0_P
DMD_HSSI0_D0_N
DMD_HSSI1_D7_P
DMD_HSSI1_D7_N
DMD_HSSI1_D5_P
DMD_HSSI1_D5_N
DMD_HSSI0_D7_P
DMD_HSSI0_D7_N
DMD_HSSI1_D0_P
DMD_HSSI1_D0_N
DMD_HSSI1_D0_P
DMD_HSSI1_D0_N
DMD_HSSI0_D0_P
DMD_HSSI0_D0_N
DMD_HSSI0_D6_P
DMD_HSSI0_D6_N
DMD_HSSI1_D0_P
DMD_HSSI1_D0_N
DMD_HSSI1_D1_P
DMD_HSSI1_D1_N
DMD_HSSI1_D1_P
DMD_HSSI1_D1_N
DMD_HSSI0_D1_P
DMD_HSSI0_D1_N
DMD_HSSI0_D7_P
DMD_HSSI0_D7_N
DMD_HSSI1_D1_P
DMD_HSSI1_D1_N
DMD_HSSI1_D2_P
DMD_HSSI1_D2_N
DMD_HSSI1_D2_P
DMD_HSSI1_D2_N
DMD_HSSI0_D2_P
DMD_HSSI0_D2_N
DMD_HSSI0_D4_P
DMD_HSSI0_D4_N
DMD_HSSI1_D2_P
DMD_HSSI1_D2_N
DMD_HSSI1_D3_P
DMD_HSSI1_D3_N
DMD_HSSI1_D3_P
DMD_HSSI1_D3_N
DMD_HSSI0_D3_P
DMD_HSSI0_D3_N
DMD_HSSI0_D5_P
DMD_HSSI0_D5_N
DMD_HSSI1_D3_P
DMD_HSSI1_D3_N
DMD_HSSI1_D4_P
DMD_HSSI1_D4_N
DMD_HSSI1_D4_P
DMD_HSSI1_D4_N
DMD_HSSI0_D4_P
DMD_HSSI0_D4_N
DMD_HSSI0_D2_P
DMD_HSSI0_D2_N
DMD_HSSI1_D4_P
DMD_HSSI1_D4_N
DMD_HSSI1_D5_P
DMD_HSSI1_D5_N
DMD_HSSI1_D5_P
DMD_HSSI1_D5_N
DMD_HSSI0_D5_P
DMD_HSSI0_D5_N
DMD_HSSI0_D3_P
DMD_HSSI0_D3_N
DMD_HSSI1_D5_P
DMD_HSSI1_D5_N
DMD_HSSI1_D6_P
DMD_HSSI1_D6_N
DMD_HSSI1_D6_P
DMD_HSSI1_D6_N
DMD_HSSI0_D6_P
DMD_HSSI0_D6_N
DMD_HSSI0_D0_P
DMD_HSSI0_D0_N
DMD_HSSI1_D6_P
DMD_HSSI1_D6_N
DMD_HSSI1_D7_P
DMD_HSSI1_D7_N
DMD_HSSI1_D7_P
DMD_HSSI1_D7_N
DMD_HSSI0_D7_P
DMD_HSSI0_D7_N
DMD_HSSI0_D1_P
DMD_HSSI0_D1_N
DMD_HSSI1_D7_P
DMD_HSSI1_D7_N