JAJSQ90 september   2020 TSB41BA3F-EP

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Revision History
  6. 5 Terminal Configuration and Functions
    1.     Terminal Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics - Driver
    6. 6.6 Electrical Characteristics - Receiver
    7. 6.7 Electrical Characteristics - Device
    8. 6.8 Switching Characteristics
  8. 7 Operating Life Deration
  9. 8 Parameter Measurement Information
  10. 9 Overview
  11. 10Functional Block Diagram
  12. 11Principles Of Operation (1394b Interface)
    1. 11.1 LLC Service Request
    2. 11.2 Status Transfer
    3. 11.3 Receive
    4. 11.4 Transmit
  13. 12Principles Of Operation (1394a-2000 Interface)
    1. 12.1 LLC Service Request
    2. 12.2 Status Transfer
    3. 12.3 Receive
    4. 12.4 Transmit
    5. 12.5 Interface Reset and Disable
  14. 13Applications, Implementation, and Layout
    1. 13.1 Known exceptions to functional specification (errata).
      1. 13.1.1 Errata # 1:Restore from Leaf Node (Nephew)
        1. 13.1.1.1 Detailed Description
        2. 13.1.1.2 Background
        3. 13.1.1.3 Workaround Proposal
        4. 13.1.1.4 Corrective Action
    2. 13.2 Application Information
      1. 13.2.1 Interoperability with earlier revisions of TSB41BA3
      2. 13.2.2 Internal Register Configuration
      3. 13.2.3 Feature Enhancements to revision F
        1. 13.2.3.1 Detect Loss of Descrambler Synchronization
          1. 13.2.3.1.1 Detect Loss of Descrambler Synchronization Advantages and Uses
        2. 13.2.3.2 Fast Retrain
          1. 13.2.3.2.1 Fast-Retrain Advantages and Uses
          2. 13.2.3.2.2 Fast-Retrain Backward Compatibility
        3. 13.2.3.3 Fast Power-On Re-connect
          1. 13.2.3.3.1 Fast Power-On Re-Connect Advantages and Uses
          2. 13.2.3.3.2 Fast Power-On Re-Connect Backward Compatibility
        4. 13.2.3.4 Fast Connection Tone Debounce
        5. 13.2.3.5 Programmable invalidCount
      4. 13.2.4 Power-Class Programming
      5. 13.2.5 Using The TSB41BA3F-EP With A 1394-1995 Or 1394a-2000 Link Layer
      6. 13.2.6 Power-Up Reset
      7. 13.2.7 Crystal Selection
      8. 13.2.8 Bus Reset
      9. 13.2.9 Designing With Powerpad™ Devices
  15. 14Device and Documentation Support
    1. 14.1 Tools and Software
    2. 14.2 Device Nomenclature
    3. 14.3 Documentation Support
    4. 14.4 サポート・リソース
    5. 14.5 Trademarks
    6. 14.6 静電気放電に関する注意事項
    7. 14.7 用語集
  16. 15Mechanical, Packaging, and Orderable Information
    1. 15.1 Packaging Information
    2. 15.2 Mechanical Data

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

13.2.5 Using The TSB41BA3F-EP With A 1394-1995 Or 1394a-2000 Link Layer

The TSB41BA3F-EP implements the PHY-LLC interface specified in the 1394b Supplement. This interface is based on the interface described in Section 17 of IEEE 1394b-2002. When using an LLC that is compliant with the IEEE 1394b-2002 interface, the BMODE input must be tied high.

The TSB41BA3F-EP also functions with an LLC that is compliant with the older 1394 standards. This interface is compatible with both the older Annex J interface specified in the IEEE Std 1394-1995 (with the exception of the Annex J isolation interfacing method) and the PHY-LLC interface specified in 1394a-2000. When using an LLC that is not compliant with the IEEE 1394b-2002 interface, the BMODE input must be tied low.

When the BMODE input is tied low, the TSB41BA3F-EP implements the PHY-LLC interface specified in the 1394a-2000 Supplement. This interface is based on the interface described in informative Annex J of IEEE Std 1394-1995, which is the interface used in the oldest Texas Instruments PHY devices. The PHY-LLC interface specified in 1394a-2000 is compatible with the older Annex J. However, the TSB41BA3F-EP does not support the Annex J isolation interfacing method. When implementing the 1394a-2000 interface, certain signals are not used:

  • The PINT output (terminal 1) can be left open.
  • The LCLK_PMC input (terminal 7) must be tied directly to ground or through a pulldown resistor of ~1 kΩ or less, unless the PMC mode is desired (see LCLK_PMC terminal description).

All other signals are connected to their counterparts on the 1394a link-layer controller. The PCLK output corresponds to the SCLK input signal on most LLCs.

The 1394a-2000 Supplement includes enhancements to the Annex J interface that should be comprehended when using the TSB41BA3F-EP with a 1394-1995 LLC device.

  • A new LLC service request was added which allows the LLC to temporarily enable and disable asynchronous arbitration accelerations. If the LLC does not implement this new service request, then the arbitration enhancements must not be enabled (see the EAA bit in PHY register 5).
  • The capability to perform multispeed concatenation (the concatenation of packets of differing speeds) was added in order to improve bus efficiency (primarily during isochronous transmission). If the LLC does not support multispeed concatenation, then multispeed concatenation must not be enabled in the PHY (see the EMC bit in PHY register 5).
  • In order to accommodate the higher transmission speeds expected in future revisions of the standard, 1394a-2000 extended the speed code in bus requests from 2 bits to 3 bits, increasing the length of the bus request from 7 bits to 8 bits. The new speed codes were carefully selected so that new 1394a-2000 PHY and LLC devices would be compatible, for speeds from S100 to S400, with legacy PHY and LLC devices that use the 2-bit speed codes. The TSB41BA3F-EP correctly interprets both 7-bit bus requests (with 2-bit speed code) and 8-bit bus requests (with 3-bit speed codes). Moreover, if a 7-bit bus request is immediately followed by another request (for example, a register read or write request), then the TSB41BA3F-EP correctly interprets both requests. Although the TSB41BA3F-EP correctly interprets 8-bit bus requests, a request with a speed code exceeding S400 while in 1394a-2000 PHY-link interface mode results in the TSB41BA3F-EP transmitting a null packet (data prefix followed by data end, with no data in the packet).