JAJSQ90 september   2020 TSB41BA3F-EP

PRODUCTION DATA  

  1.   1
  2. 特長
  3. アプリケーション
  4. 概要
  5. Revision History
  6. Terminal Configuration and Functions
    1.     Terminal Functions
  7. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics - Driver
    6. 6.6 Electrical Characteristics - Receiver
    7. 6.7 Electrical Characteristics - Device
    8. 6.8 Switching Characteristics
  8. Operating Life Deration
  9. Parameter Measurement Information
  10. Overview
  11. 10Functional Block Diagram
  12. 11Principles Of Operation (1394b Interface)
    1. 11.1 LLC Service Request
    2. 11.2 Status Transfer
    3. 11.3 Receive
    4. 11.4 Transmit
  13. 12Principles Of Operation (1394a-2000 Interface)
    1. 12.1 LLC Service Request
    2. 12.2 Status Transfer
    3. 12.3 Receive
    4. 12.4 Transmit
    5. 12.5 Interface Reset and Disable
  14. 13Applications, Implementation, and Layout
    1. 13.1 Known exceptions to functional specification (errata).
      1. 13.1.1 Errata # 1:Restore from Leaf Node (Nephew)
        1. 13.1.1.1 Detailed Description
        2. 13.1.1.2 Background
        3. 13.1.1.3 Workaround Proposal
        4. 13.1.1.4 Corrective Action
    2. 13.2 Application Information
      1. 13.2.1 Interoperability with earlier revisions of TSB41BA3
      2. 13.2.2 Internal Register Configuration
      3. 13.2.3 Feature Enhancements to revision F
        1. 13.2.3.1 Detect Loss of Descrambler Synchronization
          1. 13.2.3.1.1 Detect Loss of Descrambler Synchronization Advantages and Uses
        2. 13.2.3.2 Fast Retrain
          1. 13.2.3.2.1 Fast-Retrain Advantages and Uses
          2. 13.2.3.2.2 Fast-Retrain Backward Compatibility
        3. 13.2.3.3 Fast Power-On Re-connect
          1. 13.2.3.3.1 Fast Power-On Re-Connect Advantages and Uses
          2. 13.2.3.3.2 Fast Power-On Re-Connect Backward Compatibility
        4. 13.2.3.4 Fast Connection Tone Debounce
        5. 13.2.3.5 Programmable invalidCount
      4. 13.2.4 Power-Class Programming
      5. 13.2.5 Using The TSB41BA3F-EP With A 1394-1995 Or 1394a-2000 Link Layer
      6. 13.2.6 Power-Up Reset
      7. 13.2.7 Crystal Selection
      8. 13.2.8 Bus Reset
      9. 13.2.9 Designing With Powerpad™ Devices
  15. 14Device and Documentation Support
    1. 14.1 Tools and Software
    2. 14.2 Device Nomenclature
    3. 14.3 Documentation Support
    4. 14.4 サポート・リソース
    5. 14.5 Trademarks
    6. 14.6 静電気放電に関する注意事項
    7. 14.7 用語集
  16. 15Mechanical, Packaging, and Orderable Information
    1. 15.1 Packaging Information
    2. 15.2 Mechanical Data

パッケージ・オプション

メカニカル・データ(パッケージ|ピン)
サーマルパッド・メカニカル・データ
発注情報

Transmit

When the LLC issues a bus request through the LREQ terminal, the PHY arbitrates to gain control of the bus. If the PHY wins arbitration for the serial bus, then the PHY-LLC interface bus is granted to the LLC by asserting the grant state (11b) on the CTL terminals and the grant type on the D terminals for one PCLK cycle, followed by idle for one clock cycle. The LLC then takes control of the bus by asserting either idle (00b), hold (11b), or transmit (01b) on the CTL terminals. If the PHY does not detect a hold or transmit state within eight PCLK cycles, then the PHY takes control of the PHY-link interface. The hold state is used by the LLC to retain control of the bus while it prepares data for transmission. The LLC can assert hold for zero or more clock cycles (that is, the LLC need not assert hold before transmit). During the hold state, the LLC is expected to drive the D lines to 0. The PHY asserts data-prefix on the serial bus during this time.

When the LLC is ready to send data, the LLC asserts transmit on the CTL terminals as well as sending the first bits of packet data on the D lines. The transmit state is held on the CTL terminals until the last bits of data have been sent. The LLC then asserts either hold or idle on the CTL terminals for one clock cycle. If the hold is asserted, then the hold is immediately followed by one clock cycle of idle. The link then releases the PHY-link interface by putting the CTL and D terminals in a high-impedance state. The PHY then regains control of the PHY-link interface.

GUID-79E267B1-DF58-4773-9A6E-47359FEEDAA6-low.gifFigure 12-14 Transmit Packet Timing With Optional Link Request

The hold state asserted at the end of packet transmission allows the LLC to make an additional link request for packet transmission and/or to notify the PHY that the packet marks the end of a subaction. The link requests allowed after packet transmission are listed in Table 12-33 (note that the link request types allowed during this period are a subset of all of the allowed types of link requests—see Table 11-4). The associated speed codes and packet format are listed in Table 12-33 and Table 12-34, respectively. If the LLC requests to send an additional packet, then the PHY does not necessarily have to grant the request. If the LLC is notifying the PHY of the end of a subaction, then the LLC sets D4 during the hold state at the end of packet transmission.

Table 12-33 Link Request Type Encoding During Packet Transmission
D1–D3Request Type
000No request
001Isoch_Req_Odd
010Isoch_Req_Even
011Current
100Next_Even
101Next_Odd
110Cyc_Start_Req
111Reserved
Table 12-34 Link Request Speed Code Encoding During Packet Transmission
D5–D6DATA RATE
00S100
01S200
10S400
11S800
Table 12-35 Link Request Format Encoding During Packet Transmission
D0FORMAT
0Link does not request either Beta or legacy packet format for bus transmission.
1Link requests Beta packet format for bus transmission.
Table 12-36 Subaction End Notification Encoding During Packet Transmission
D4DESCRIPTION
0Transmitted packet does not represent end of a subaction.
1Transmitted packet marks the end of a subaction.

The PHY indicates to the link during the GRANT cycle which type of grant is being issued. This indication includes the grant type as well as the grant speed. The link uses the bus grant for transmitting the granted packet type. The link transmits a granted packet type only if its request type exactly matches the granted speed and the granted format.

Table 12-37 Format Type During Grant Cycle
D0 VALUE DURING
GRANT CYCLE
FORMAT
0Unspecified
1Beta format
Table 12-38 Grant Type Values During Grant Cycle
[D1–D3] VALUE DURING
GRANT CYCLE
REQUEST TYPE
000Reserved
001Reserved
010Isochronous grant
011Reserved
100Reserved
101Asynchronous grant
110Cycle start grant
111Immediate grant
Table 12-39 Speed Type Values During Grant Cycle
[D5–D6] VALUE DURING
GRANT CYCLE
SPEED TYPE
00S100
01S200
10S400
11S800