JAJSQ90 september 2020 TSB41BA3F-EP
PRODUCTION DATA
Whenever the PHY detects the data-prefix state on the serial bus, it initiates a receive operation by asserting receive on the CTL terminals and a logic 1 on each of the D bus terminals (data-on indication). The PHY indicates the start of a packet by placing the speed code (encoded as shown in Table 12-11) on the D terminals, followed by packet data. The PHY holds the CTL terminals in the receive state until the last symbol of the packet has been transferred. The PHY indicates the end of packet data by asserting idle on the CTL terminals. All received packets are transferred to the LLC. Note that the speed code is part of the PHY-LLC protocol and is not included in the calculation of CRC or any other data protection mechanisms.
It is possible for the PHY to receive a null packet, which consists of the data-prefix state on the serial bus followed by the data-end state, without any packet data. A null packet is transmitted whenever the packet speed exceeds the capability of the receiving PHY, or whenever the LLC immediately releases the bus without transmitting any data. In this case, the PHY asserts receive on the CTL terminals with the data-on indication (all 1s) on the D bus terminals, followed by Idle on the CTL terminals, without any speed code or data being transferred. In all cases, in normal operation, the TSB41BA3F-EP sends at least one data-on indication before sending the speed code or terminating the receive operation.
The TSB41BA3F-EP also transfers its own self-ID packet, transmitted during the self-ID phase of bus initialization, to the LLC. This packet is transferred to the LLC just as any other received self-ID packet.
The sequence of events for a normal packet reception is as follows:
The sequence of events for a null packet reception is as follows:
D0–D7(1) | DATA RATE |
---|---|
00XX XXXX | S100 |
0100 XXXX | S200 |
0101 0000 | S400 |
11YY YYYY | data-on indication |