To request access to the bus, to read or write a PHY register, or to send a link notification to PHY, the LLC sends a serial bit stream on the LREQ terminal as shown in Figure 11-2.

Figure 11-2 LREQ Request Stream

The length of the stream varies depending on the type of request as shown in Table 11-3.

Regardless of the type of request, a start bit of 1 is required at the beginning of the stream and a stop bit of 0 is required at the end of the stream. The second through fifth bits of the request stream indicate the type of the request. In the following descriptions, bit LR1 is the most significant and is transmitted first in the request bit stream. The LREQ terminal is normally low.

Table 11-4 shows the encoding for the request type.

For a bus request, the length of the LREQ bit stream is 11 bits as shown in Table 11-5.

Table 11-6 shows the 1-bit request format field used in bus requests.

Table 11-7 shows the 4-bit request speed field used in bus requests.

For a read register request, the length of the LREQ bit stream is 10 bits as shown in Table 11-8.

For a write register request, the length of the LREQ bit stream is 18 bits as shown in Table 11-9.

For a link notification request, the length of the LREQ bit stream is 6 bits as shown in Table 11-10.

For fair or priority access, the LLC sends a bus request at least one clock after the PHY-LLC interface becomes idle. The PHY queues all bus requests and can queue one request of each type. If the LLC issues a different request of the same type, then the new request overwrites any nonserviced request of that type. On the receipt (CTL terminals are asserted to the receive state, 10b) of a packet, queued requests are not cleared by the PHY.

The cycle master node uses a cycle start request (Cyc_Start_Req) to send a cycle start message. After receiving or transmitting a cycle start message, the LLC can issue an isochronous bus request (IsoReq). The PHY clears an isochronous request only when the serial bus has been won.

To send an acknowledge packet, the LLC must issue an immediate bus request (Immed_Req) during the reception of the packet addressed to it. This is required in order to minimize the idle gap between the end of the received packet and the start of the transmitted acknowledge packet. As soon as the received packet ends, the PHY immediately grants control of the bus to the LLC. The LLC sends an acknowledgment to the sender unless the header CRC of the received packet is corrupted. In this case, the LLC does not transmit an acknowledge, but instead cancels the transmit operation and releases the interface immediately; the LLC must not use this grant to send another type of packet. After the interface is released the LLC can proceed with another request.

For write register requests, the PHY loads the specified data into the addressed register as soon as the request transfer is complete. For read register requests, the PHY returns the contents of the addressed register to the LLC at the next opportunity through a PHY status transfer. A write or read register request can be made at any time, including while a bus request is pending. Once a read register request is made, the PHY ignores further read register requests until the register contents are successfully transferred to the LLC. A bus reset does not clear a pending read register request.