JAJSLB2E November   2014  – May 2025 DLP9500UV

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 説明
  5. 4 概要 (続き)
  6. 5 Pin Configuration and Functions
    1.     Pin Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  Storage Conditions
    3. 6.3  ESD Ratings
    4. 6.4  Recommended Operating Conditions
    5. 6.5  Thermal Information
    6. 6.6  Electrical Characteristics
    7. 6.7  LVDS Timing Requirements
    8. 6.8  LVDS Waveform Requirements
    9. 6.9  Serial Control Bus Timing Requirements
    10. 6.10 Systems Mounting Interface Loads
    11. 6.11 Micromirror Array Physical Characteristics
    12. 6.12 Micromirror Array Optical Characteristics
    13. 6.13 Chipset Component Usage Specification
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 DLPC410—Digital Controller for DLP Discovery 4100 Chipset
      2. 7.3.2 DLPA200 - DMD Micromirror Drivers
      3. 7.3.3 DLPR410—PROM for DLP Discovery 4100 Chipset
      4. 7.3.4 DLP9500—DLP 0.95 1080p 2xLVDS UV Type-A DMD 1080p DMD
        1. 7.3.4.1 DLP9500UV 1080p Chipset Interfaces
          1. 7.3.4.1.1 DLPC410 Interface Description
            1. 7.3.4.1.1.1 DLPC410 IO
            2. 7.3.4.1.1.2 Initialization
            3. 7.3.4.1.1.3 DMD Device Detection
            4. 7.3.4.1.1.4 Power Down
          2. 7.3.4.1.2 DLPC410 to DMD Interface
            1. 7.3.4.1.2.1 DLPC410 to DMD IO Description
            2. 7.3.4.1.2.2 Data Flow
          3. 7.3.4.1.3 DLPC410 to DLPA200 Interface
            1. 7.3.4.1.3.1 DLPA200 Operation
            2. 7.3.4.1.3.2 DLPC410 to DLPA200 IO Description
          4. 7.3.4.1.4 DLPA200 to DLP9500UV Interface
            1. 7.3.4.1.4.1 DLPA200 to DLP9500UV Interface Overview
      5. 7.3.5 Measurement Conditions
    4. 7.4 Device Functional Modes
      1. 7.4.1 Single Block Mode
      2. 7.4.2 Dual Block Mode
      3. 7.4.3 Quad Block Mode
      4. 7.4.4 Global Block Mode
    5. 7.5 Window Characteristics and Optics
      1. 7.5.1 Optical Interface and System Image Quality
      2. 7.5.2 Numerical Aperture and Stray Light Control
      3. 7.5.3 Pupil Match
      4. 7.5.4 Illumination Overfill
    6. 7.6 Micromirror Array Temperature Calculation
      1. 7.6.1 Package Thermal Resistance
      2. 7.6.2 Case Temperature
      3. 7.6.3 Micromirror Array Temperature Calculation
    7. 7.7 Micromirror Landed-On and Landed-Off Duty Cycle
      1. 7.7.1 Definition of Micromirror Landed-On/Landed-Off Duty Cycle
      2. 7.7.2 Landed Duty Cycle and Useful Life of the DMD
      3. 7.7.3 Landed Duty Cycle and Operational DMD Temperature
      4. 7.7.4 Estimating the Long-Term Average Landed Duty Cycle of a Product or Application
  9. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 DMD Reflectivity Characteristics
        1. 8.1.1.1 Design Considerations Influencing DMD Reflectivity
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
        1. 8.2.1.1 Device Description
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
    3. 8.3 Power Supply Recommendations
      1. 8.3.1 Power-Up Sequence (Handled by the DLPC410)
      2. 8.3.2 DMD Power-Up and Power-Down Procedures
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
        1. 8.4.1.1 Impedance Requirements
        2. 8.4.1.2 PCB Signal Routing
        3. 8.4.1.3 Fiducials
        4. 8.4.1.4 PCB Layout Guidelines
          1. 8.4.1.4.1 DMD Interface
            1. 8.4.1.4.1.1 Trace Length Matching
          2. 8.4.1.4.2 DLP9500UV Decoupling
            1. 8.4.1.4.2.1 Decoupling Capacitors
          3. 8.4.1.4.3 VCC and VCC2
          4. 8.4.1.4.4 DMD Layout
          5. 8.4.1.4.5 DLPA200
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Device Nomenclature
      2. 9.1.2 Device Marking
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 Related Links
    4. 9.4 サポート・リソース
    5. 9.5 Trademarks
    6. 9.6 静電気放電に関する注意事項
    7. 9.7 用語集
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information
8.4.1.4.2 DLP9500UV Decoupling

General decoupling capacitors for the DLP9500UV should be distributed around the PCB and placed to minimize the distance from IC voltage and ground pads. Each decoupling capacitor (0.1µF recommended) should have vias directly to the ground and power planes. Via sharing between components (discreet or integrated) is discouraged. The power and ground pads of the DLP9500UV should be tied to the voltage and ground planes with their vias.