SLAAEO4 November   2025 MSPM0G3507 , MSPM0L1306

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1 Introduction
    1. 1.1 Terminology
  5. 2 NONMAIN Architecture
    1. 2.1 MSPM0 Family Overview
    2. 2.2 NONMAIN Configuration Overview
    3. 2.3 NONMAIN Memory
  6. 3 NONMAIN Configuration
    1. 3.1 BCR Configuration
      1. 3.1.1 BCR Configuration ID
      2. 3.1.2 Serial Wire Debug (SWD) Policy
        1. 3.1.2.1 Access Policy
        2. 3.1.2.2 Debug Policy
          1. 3.1.2.2.1 Plain Text Password Example
          2. 3.1.2.2.2 SHA2-256 Password Example
        3. 3.1.2.3 Mass Erase and Factory Reset Policy
        4. 3.1.2.4 TI Failure Analysis
      3. 3.1.3 Flash Memory Static Write Protection
        1. 3.1.3.1 MAIN Flash Static Write Protection
        2. 3.1.3.2 NONMAIN Flash Static Write Protection
      4. 3.1.4 Customer Secure Code (CSC)
        1. 3.1.4.1 CSC Policy
        2. 3.1.4.2 Flash Bank Swap Policy
        3. 3.1.4.3 Debug Hold
      5. 3.1.5 Fast Boot Mode
      6. 3.1.6 Application Digest Check
        1. 3.1.6.1 CRC32 Digest Check Example
        2. 3.1.6.2 SHA2-256 Digest Check Example
      7. 3.1.7 BSL Policy
      8. 3.1.8 BCR Checksum
        1. 3.1.8.1 CRC Check Fail Handling
    2. 3.2 BSL Configuration
      1. 3.2.1 BSL Configuration ID
      2. 3.2.2 Invoke Pin Configuration
      3. 3.2.3 ROM-Based Communication Interface
        1. 3.2.3.1 UART Interface
        2. 3.2.3.2 I2C Interface
        3. 3.2.3.3 USB Interface
      4. 3.2.4 Flash Plug-in Interface
      5. 3.2.5 Alternative BSL Interface
      6. 3.2.6 BSL Security Configuration
        1. 3.2.6.1 Access Password
        2. 3.2.6.2 Read-Out Feature
        3. 3.2.6.3 Alert Feature
        4. 3.2.6.4 Application Integrity Check
      7. 3.2.7 BSL Checksum
        1. 3.2.7.1 CRC Check Fail Handling
  7. 4 NONMAIN Configuration With SysConfig
    1. 4.1 SysConfig Introduction
    2. 4.2 BCR Configuration with SysConfig
      1. 4.2.1 Password Configuration
      2. 4.2.2 Flash Static Write Protection
      3. 4.2.3 Other BCR Configurations
    3. 4.3 BSL Configuration With SysConfig
      1. 4.3.1 BSL Access Password
      2. 4.3.2 BSL Invoke Pin Configuration
      3. 4.3.3 BSL Communication Interface
      4. 4.3.4 Flash Plug-in Interface
      5. 4.3.5 Alternative BSL Interface
      6. 4.3.6 Other BCR Configurations
  8. 5 NONMAIN Configuration in Application Code
  9. 6 NONMAIN Operation with IDE Tool
    1. 6.1 NONMAIN Configuration Files
    2. 6.2 Project Erase Property
    3. 6.3 Password-Protected Debug
  10. 7 NONMAIN Operation with Programmer Tool
    1. 7.1 NONMAIN Operation with UniFlash
    2. 7.2 NONMAIN Operation with J-Flash
    3. 7.3 NONMAIN Operation with C-GANG
    4. 7.4 NONMAIN Operation with MSP-GANG
  11. 8 Frequently Asked Questions (FAQs)
    1. 8.1 MCU Locked State Analysis
      1. 8.1.1 Hardware Issue Analysis
        1. 8.1.1.1 Hardware Circuit Design
        2. 8.1.1.2 Debugger Connection
        3. 8.1.1.3 External Reset Signal
      2. 8.1.2 Software Issue Analysis
        1. 8.1.2.1 CPU Enters a Fault State
        2. 8.1.2.2 BCR Configuration
        3. 8.1.2.3 Low Power Mode (STOP or STANDBY)
        4. 8.1.2.4 SHUTDOWN IO State
        5. 8.1.2.5 SWD IO Function
        6. 8.1.2.6 WDT or IWDT Reset
        7. 8.1.2.7 Software POR or BOOTRST
    2. 8.2 Unlock the MSPM0 Device
      1. 8.2.1 Force MCU to Enter BSL Mode
      2. 8.2.2 Send BSL Command
      3. 8.2.3 Generate DSSM Command
    3. 8.3 Debug Error Overview
      1. 8.3.1 No Error Code: DAP Connection Error
      2. 8.3.2 No Error Code: Connection to MSPM0 Core Failed
      3. 8.3.3 Error - 6305: PRSC Module Failed to Write a Routine Register
      4. 8.3.4 Error - 260: An Attempt to Connect to the XDS110 Failed
      5. 8.3.5 Error - 261: Invalid Response From the XDS110
      6. 8.3.6 Error - 615: Target Fails to Identify a Correctly Formatted SWD Header
      7. 8.3.7 Error - 1001: Requested Operation is not Supported on This Device
      8. 8.3.8 Error - 2131: Unable to Access Device Register
    4. 8.4 MSPM0 Boot Diagnostic
  12. 9 Summary
  13. 10References

1 Introduction

Figure 1-1 shows the common platform memory map that all MSPM0 devices share. The map has four different memory regions.

  • MAIN Flash
  • NONMAIN Flash
  • FACTORY Region
  • ROM
MSPM0 MSPM0 Memory MapFigure 1-1 MSPM0 Memory Map

MAIN flash is the memory used to store executable code and data. The MSPM0 device supports single bank or dual bank MAIN flash, see the device-specific data sheet for more details.

NONMAIN flash is a dedicated region of flash memory which stores the configuration data used by the boot configuration routine (BCR) configuration and bootstrap loader (BSL) configuration to boot the device. The BCR and BSL have configuration policies which can remain at the default values (as is typical during development and evaluation), or modified for specific purposes (as is typical during production programming) by altering the values programmed into the NONMAIN flash region.

Note: After erasing the NONMAIN flash, verify that the proper value loads into the NONMAIN flash. Failure to verify the load results in permanently locking the device after the next BOOTRST.

FACTORY region is a memory-mapped flash region which provides read-only data describing the capabilities of a device, as well as any factory-provided trim information for use by application software.

The read-only memory (ROM) consists of an immutable root-of-trust boot configuration routine (BCR) and bootstrap loader (BSL). The BCR is always the first code to run on the Cortex-M0+ processor following a BOOTRST of the device before the main application starts. The BCR also runs using hardware or software invocation of the bootstrap loader (BSL) and authorizes the BSL entry. Figure 1-2 shows the high level boot flow for MSPM0 devices. For more details, refer to the Cybersecurity Enablers in MSPM0 MCUs application note.

MSPM0 MSPM0 Boot FlowFigure 1-2 MSPM0 Boot Flow

The BCR sets up the device security policies, configures the device for operation, and optionally starts the BSL if ROM or Flash BSL presents. If the BCR starts the BSL, use the BSL to program or verify the device memory (flash and SRAM) using a standard serial interface (UART or I2C).