SLAAEO4 November   2025 MSPM0G3507 , MSPM0L1306

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1 Introduction
    1. 1.1 Terminology
  5. 2 NONMAIN Architecture
    1. 2.1 MSPM0 Family Overview
    2. 2.2 NONMAIN Configuration Overview
    3. 2.3 NONMAIN Memory
  6. 3 NONMAIN Configuration
    1. 3.1 BCR Configuration
      1. 3.1.1 BCR Configuration ID
      2. 3.1.2 Serial Wire Debug (SWD) Policy
        1. 3.1.2.1 Access Policy
        2. 3.1.2.2 Debug Policy
          1. 3.1.2.2.1 Plain Text Password Example
          2. 3.1.2.2.2 SHA2-256 Password Example
        3. 3.1.2.3 Mass Erase and Factory Reset Policy
        4. 3.1.2.4 TI Failure Analysis
      3. 3.1.3 Flash Memory Static Write Protection
        1. 3.1.3.1 MAIN Flash Static Write Protection
        2. 3.1.3.2 NONMAIN Flash Static Write Protection
      4. 3.1.4 Customer Secure Code (CSC)
        1. 3.1.4.1 CSC Policy
        2. 3.1.4.2 Flash Bank Swap Policy
        3. 3.1.4.3 Debug Hold
      5. 3.1.5 Fast Boot Mode
      6. 3.1.6 Application Digest Check
        1. 3.1.6.1 CRC32 Digest Check Example
        2. 3.1.6.2 SHA2-256 Digest Check Example
      7. 3.1.7 BSL Policy
      8. 3.1.8 BCR Checksum
        1. 3.1.8.1 CRC Check Fail Handling
    2. 3.2 BSL Configuration
      1. 3.2.1 BSL Configuration ID
      2. 3.2.2 Invoke Pin Configuration
      3. 3.2.3 ROM-Based Communication Interface
        1. 3.2.3.1 UART Interface
        2. 3.2.3.2 I2C Interface
        3. 3.2.3.3 USB Interface
      4. 3.2.4 Flash Plug-in Interface
      5. 3.2.5 Alternative BSL Interface
      6. 3.2.6 BSL Security Configuration
        1. 3.2.6.1 Access Password
        2. 3.2.6.2 Read-Out Feature
        3. 3.2.6.3 Alert Feature
        4. 3.2.6.4 Application Integrity Check
      7. 3.2.7 BSL Checksum
        1. 3.2.7.1 CRC Check Fail Handling
  7. 4 NONMAIN Configuration With SysConfig
    1. 4.1 SysConfig Introduction
    2. 4.2 BCR Configuration with SysConfig
      1. 4.2.1 Password Configuration
      2. 4.2.2 Flash Static Write Protection
      3. 4.2.3 Other BCR Configurations
    3. 4.3 BSL Configuration With SysConfig
      1. 4.3.1 BSL Access Password
      2. 4.3.2 BSL Invoke Pin Configuration
      3. 4.3.3 BSL Communication Interface
      4. 4.3.4 Flash Plug-in Interface
      5. 4.3.5 Alternative BSL Interface
      6. 4.3.6 Other BCR Configurations
  8. 5 NONMAIN Configuration in Application Code
  9. 6 NONMAIN Operation with IDE Tool
    1. 6.1 NONMAIN Configuration Files
    2. 6.2 Project Erase Property
    3. 6.3 Password-Protected Debug
  10. 7 NONMAIN Operation with Programmer Tool
    1. 7.1 NONMAIN Operation with UniFlash
    2. 7.2 NONMAIN Operation with J-Flash
    3. 7.3 NONMAIN Operation with C-GANG
    4. 7.4 NONMAIN Operation with MSP-GANG
  11. 8 Frequently Asked Questions (FAQs)
    1. 8.1 MCU Locked State Analysis
      1. 8.1.1 Hardware Issue Analysis
        1. 8.1.1.1 Hardware Circuit Design
        2. 8.1.1.2 Debugger Connection
        3. 8.1.1.3 External Reset Signal
      2. 8.1.2 Software Issue Analysis
        1. 8.1.2.1 CPU Enters a Fault State
        2. 8.1.2.2 BCR Configuration
        3. 8.1.2.3 Low Power Mode (STOP or STANDBY)
        4. 8.1.2.4 SHUTDOWN IO State
        5. 8.1.2.5 SWD IO Function
        6. 8.1.2.6 WDT or IWDT Reset
        7. 8.1.2.7 Software POR or BOOTRST
    2. 8.2 Unlock the MSPM0 Device
      1. 8.2.1 Force MCU to Enter BSL Mode
      2. 8.2.2 Send BSL Command
      3. 8.2.3 Generate DSSM Command
    3. 8.3 Debug Error Overview
      1. 8.3.1 No Error Code: DAP Connection Error
      2. 8.3.2 No Error Code: Connection to MSPM0 Core Failed
      3. 8.3.3 Error - 6305: PRSC Module Failed to Write a Routine Register
      4. 8.3.4 Error - 260: An Attempt to Connect to the XDS110 Failed
      5. 8.3.5 Error - 261: Invalid Response From the XDS110
      6. 8.3.6 Error - 615: Target Fails to Identify a Correctly Formatted SWD Header
      7. 8.3.7 Error - 1001: Requested Operation is not Supported on This Device
      8. 8.3.8 Error - 2131: Unable to Access Device Register
    4. 8.4 MSPM0 Boot Diagnostic
  12. 9 Summary
  13. 10References

3.1.2 Serial Wire Debug (SWD) Policy

The serial wire debug (SWD) related policies configure the available functions in the physical debug interface of the device. MSPM0 devices support three generic security levels: no restrictions (Level 0), custom restrictions (Level 1), and fully restricted (Level 2). Table 3-2 shows the three generic security levels, from least restrictive to most restrictive, including the differences between each level.

Table 3-2 Generic Security Levels
LevelScenarioSW-DP Access PolicyAPP Debug PolicyMass Erase PolicyFactory Reset PolicyTI FA Policy
0No restrictionsENENEN,DIS(1)ENEN
1Custom restrictionsENEN, EN with PW, DISEN, EN with PWDISEN, EN with PW,DISEN, DIS
2Fully restrictedDISDo not care(2)(access in not possible when SW-DP is disabled)
(1) MSPM0C1103/4 does not support mass erase operations.
(2) When the SW-DP policy is SW-DP disabled, the mass erase and factory reset policies are a don't care from the point of view of the SWD interface. However, if the bootstrap loader (BSL) is enabled, the mass erase and factory reset policies do impact the available BSL functions. See the BSL security section (Section 3.2.6) for details on securing the BSL.

By default, TI provides MSPM0 in an unrestricted state. The unrestricted state allows for easy production programming, evaluation, and development. However, this unrestricted state is not recommended for mass production, as the unrestricted states leaves a large attack surface present.

There are 4 main uses of the SWD interface to take into consideration when determining protection needs:

  • Application debug access: Debugging in the IDE tool
  • Mass erase access: Erase the MAIN memory region
  • Factory reset access: Erase the MAIN memory region and reset the NONMAIN device configuration memory to TI factory defaults (Level 0)
  • TI failure analysis access: Ability for TI to initiate a failure analysis

The SWD security policies are implemented as 16-bit pattern-match fields in the NONMAIN memory, with the following characteristics:

  • An exact pattern match is required to enable lower security states
  • Any value in the 16-bit field mismatching the exact defined patterns results in a maximally secure state for the respective parameter

SWD also supports customizing four sets of passwords (128 bits in total), used to unlock device using a debug subsystem mailbox (DSSM) command. See the Hardware Programming and Debugger Guide for MSPM0 application note for detailed instructions.