SLAU144K December 2004 – August 2022 MSP430AFE221 , MSP430AFE222 , MSP430AFE223 , MSP430AFE231 , MSP430AFE232 , MSP430AFE233 , MSP430AFE251 , MSP430AFE252 , MSP430AFE253 , MSP430F2001 , MSP430F2002 , MSP430F2003 , MSP430F2011 , MSP430F2012 , MSP430F2013 , MSP430F2101 , MSP430F2111 , MSP430F2112 , MSP430F2121 , MSP430F2122 , MSP430F2131 , MSP430F2132 , MSP430F2132-EP , MSP430F2232 , MSP430F2234 , MSP430F2252 , MSP430F2252-Q1 , MSP430F2254 , MSP430F2272 , MSP430F2272-Q1 , MSP430F2274 , MSP430F2274-EP , MSP430F233 , MSP430F2330 , MSP430F235 , MSP430F2350 , MSP430F2370 , MSP430F2410 , MSP430F2416 , MSP430F2417 , MSP430F2418 , MSP430F2419 , MSP430F247 , MSP430F2471 , MSP430F248 , MSP430F2481 , MSP430F249 , MSP430F2491 , MSP430F2616 , MSP430F2617 , MSP430F2618 , MSP430F2619 , MSP430G2001 , MSP430G2101 , MSP430G2102 , MSP430G2111 , MSP430G2112 , MSP430G2121 , MSP430G2131 , MSP430G2132 , MSP430G2152 , MSP430G2153 , MSP430G2201 , MSP430G2201-Q1 , MSP430G2202 , MSP430G2203 , MSP430G2210 , MSP430G2211 , MSP430G2212 , MSP430G2213 , MSP430G2221 , MSP430G2230 , MSP430G2231 , MSP430G2231-Q1 , MSP430G2232 , MSP430G2233 , MSP430G2252 , MSP430G2253 , MSP430G2302 , MSP430G2303 , MSP430G2312 , MSP430G2313 , MSP430G2332 , MSP430G2333 , MSP430G2352 , MSP430G2353 , MSP430G2402 , MSP430G2403 , MSP430G2412 , MSP430G2413 , MSP430G2432 , MSP430G2433 , MSP430G2444 , MSP430G2452 , MSP430G2453 , MSP430G2513 , MSP430G2533 , MSP430G2544 , MSP430G2553 , MSP430G2744 , MSP430G2755 , MSP430G2855 , MSP430G2955 , MSP430TCH5E
The register mode extension word is shown in Figure 4-24 and described in Table 4-11. An example is shown in Figure 4-26.
Bit | Description | ||
---|---|---|---|
15:11 | Extension word op-code. Op-codes 1800h to 1FFFh are extension words. | ||
10:9 | Reserved | ||
ZC | Zero carry | ||
0 | The executed instruction uses the status of the carry bit C. | ||
1 | The executed instruction uses the carry bit as 0. The carry bit is defined by the result of the final operation after instruction execution. | ||
# | Repetition | ||
0 | The number of instruction repetitions is set by extension word bits 3:0. | ||
1 | The number of instruction repetitions is defined by the value of the four LSBs of Rn. See description for bits 3:0. | ||
A/L | Data length extension. Together with the B/W bits of the following MSP430 instruction, the AL bit defines the used data length of the instruction. | ||
A/L | B/W | Comment | |
0 | 0 | Reserved | |
0 | 1 | 20-bit address word | |
1 | 0 | 16-bit word | |
1 | 1 | 8-bit byte | |
5:4 | Reserved | ||
3:0 | Repetition count | ||
# = 0 | These four bits set the repetition count n. These bits contain n – 1. | ||
# = 1 | These four bits define the CPU register whose bits 3:0 set the number of repetitions. Rn.3:0 contain n – 1. |