SLAU144K December 2004 – August 2022 MSP430AFE221 , MSP430AFE222 , MSP430AFE223 , MSP430AFE231 , MSP430AFE232 , MSP430AFE233 , MSP430AFE251 , MSP430AFE252 , MSP430AFE253 , MSP430F2001 , MSP430F2002 , MSP430F2003 , MSP430F2011 , MSP430F2012 , MSP430F2013 , MSP430F2101 , MSP430F2111 , MSP430F2112 , MSP430F2121 , MSP430F2122 , MSP430F2131 , MSP430F2132 , MSP430F2132-EP , MSP430F2232 , MSP430F2234 , MSP430F2252 , MSP430F2252-Q1 , MSP430F2254 , MSP430F2272 , MSP430F2272-Q1 , MSP430F2274 , MSP430F2274-EP , MSP430F233 , MSP430F2330 , MSP430F235 , MSP430F2350 , MSP430F2370 , MSP430F2410 , MSP430F2416 , MSP430F2417 , MSP430F2418 , MSP430F2419 , MSP430F247 , MSP430F2471 , MSP430F248 , MSP430F2481 , MSP430F249 , MSP430F2491 , MSP430F2616 , MSP430F2617 , MSP430F2618 , MSP430F2619 , MSP430G2001 , MSP430G2101 , MSP430G2102 , MSP430G2111 , MSP430G2112 , MSP430G2121 , MSP430G2131 , MSP430G2132 , MSP430G2152 , MSP430G2153 , MSP430G2201 , MSP430G2201-Q1 , MSP430G2202 , MSP430G2203 , MSP430G2210 , MSP430G2211 , MSP430G2212 , MSP430G2213 , MSP430G2221 , MSP430G2230 , MSP430G2231 , MSP430G2231-Q1 , MSP430G2232 , MSP430G2233 , MSP430G2252 , MSP430G2253 , MSP430G2302 , MSP430G2303 , MSP430G2312 , MSP430G2313 , MSP430G2332 , MSP430G2333 , MSP430G2352 , MSP430G2353 , MSP430G2402 , MSP430G2403 , MSP430G2412 , MSP430G2413 , MSP430G2432 , MSP430G2433 , MSP430G2444 , MSP430G2452 , MSP430G2453 , MSP430G2513 , MSP430G2533 , MSP430G2544 , MSP430G2553 , MSP430G2744 , MSP430G2755 , MSP430G2855 , MSP430G2955 , MSP430TCH5E
Table 19-1 lists the memory-mapped registers for USART0 and USART1 in SPI mode.
Address | Acronym | Register Name | Type | Reset | Section |
---|---|---|---|---|---|
70h | U0CTL | USART0 control | Read/write | 01h with PUC | Section 19.4.1 |
71h | U0TCTL | USART0 transmit control | Read/write | 01h with PUC | Section 19.4.2 |
72h | U0RCTL | USART0 receive control | Read/write | 00h with PUC | Section 19.4.3 |
73h | U0MCTL | USART0 modulation control | Read/write | Unchanged | Section 19.4.6 |
74h | U0BR0 | USART0 baud-rate control 0 | Read/write | Unchanged | Section 19.4.4 |
75h | U0BR1 | USART0 baud-rate control 1 | Read/write | Unchanged | Section 19.4.5 |
76h | U0RXBUF | USART0 receive buffer | Read | Unchanged | Section 19.4.7 |
77h | U0TXBUF | USART0 transmit buffer | Read/write | Unchanged | Section 19.4.8 |
4h | ME1 | SFR module enable 1 | Read/write | 00h with PUC | Section 19.4.9 |
0h | IE1 | SFR interrupt enable 1 | Read/write | 00h with PUC | Section 19.4.11 |
2h | IFG1 | SFR interrupt flag 1 | Read/write | 82h with PUC | Section 19.4.13 |
78h | U1CTL | USART1 control | Read/write | 01h with PUC | Section 19.4.2 |
79h | U1TCTL | USART1 transmit control | Read/write | 01h with PUC | Section 19.4.2 |
7Ah | U1RCTL | USART1 receive control | Read/write | 00h with PUC | Section 19.4.3 |
7Bh | U1MCTL | USART1 modulation control | Read/write | Unchanged | Section 19.4.6 |
7Ch | U1BR0 | USART1 baud-rate control 0 | Read/write | Unchanged | Section 19.4.4 |
7Dh | U1BR1 | USART1 baud-rate control 1 | Read/write | Unchanged | Section 19.4.5 |
7Eh | U1RXBUF | USART1 receive buffer | Read | Unchanged | Section 19.4.7 |
7Fh | U1TXBUF | USART1 transmit buffer | Read/write | Unchanged | Section 19.4.8 |
5h | ME2 | SFR module enable 2 | Read/write | 00h with PUC | Section 19.4.10 |
1h | IE2 | SFR interrupt enable 2 | Read/write | 00h with PUC | Section 19.4.12 |
3h | IFG2 | SFR interrupt flag 2 | Read/write | 20h with PUC | Section 19.4.14 |
Modifying the SFR bits
To avoid modifying control bits for other modules, TI recommends setting or clearing the IEx and IFGx bits using BIS.B or BIC.B instructions, rather than MOV.B or CLR.B instructions.
USARTx Control Register
UxCTL is shown in Figure 19-13 and described in Table 19-2.
Return to Table 19-1.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Unused | I2C | CHAR | LISTEN | SYNC | MM | SWRST | |
rw-0 | rw-0 | rw-0 | rw-0 | rw-0 | rw-0 | rw-0 | rw-1 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-6 | Unused | R/W | 0h | Unused |
5 | I2C | R/W | 0h | I2C mode enable. This bit selects I2C or SPI operation when SYNC = 1. 0b = SPI mode 1b = I2C mode |
4 | CHAR | R/W | 0h | Character length 0b = 7-bit data 1b = 8-bit data |
3 | LISTEN | R/W | 0h | Listen enable. The LISTEN bit selects the loopback mode. 0b = Disabled 1b = Enabled. The transmit signal is internally fed back to the receiver. |
2 | SYNC | R/W | 0h | Synchronous mode enable 0b = UART mode 1b = SPI mode |
1 | MM | R/W | 0h | Master mode 0b = USART is slave 1b = USART is master |
0 | SWRST | R/W | 1h | Software reset enable 0b = Disabled. USART reset released for operation. 1b = Enabled. USART logic held in reset state. |
USARTx Transmit Control Register
UxTCTL is shown in Figure 19-14 and described in Table 19-3.
Return to Table 19-1.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CKPH | CKPL | SSELx | Unused | STC | TXEPT | ||
rw-0 | rw-0 | rw-0 | rw-0 | rw-0 | rw-0 | rw-0 | rw-1 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | CKPH | R/W | 0h | Clock phase select 0b = Data is changed on the first UCLK edge and captured on the following edge. 1b = Data is captured on the first UCLK edge and changed on the following edge. |
6 | CKPL | R/W | 0h | Clock polarity select 0b = The inactive state is low. 1b = The inactive state is high. |
5-4 | SSELx | R/W | 0h | Source select. These bits select the BRCLK source clock. 00b = External UCLK (valid for slave mode only) 01b = ACLK (valid for master mode only) 10b = SMCLK (valid for master mode only) 11b = SMCLK (valid for master mode only) |
3-2 | Unused | R/W | 0h | |
1 | STC | R/W | 0h | Slave transmit control 0b = 4-pin SPI mode: STE enabled 1b = 3-pin SPI mode: STE disabled |
0 | TXEPT | R/W | 1h | Transmitter empty flag. The TXEPT flag is not used in slave mode. 0b = Transmission active and/or data waiting in UxTXBUF 1b = UxTXBUF and TX shift register are empty |
USARTx Receive Control Register
UxRCTL is shown in Figure 19-15 and described in Table 19-4.
Return to Table 19-1.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FE | Unused | OE | Unused | ||||
rw-0 | rw-0 | rw-0 | rw-0 | rw-0 | rw-0 | rw-0 | rw-0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | FE | R/W | 0h | Framing error flag. This bit indicates a bus conflict when MM = 1 and STC = 0. FE is unused in slave mode. 0b = No conflict detected 1b = A negative edge occurred on STE, indicating bus conflict. |
6 | Unused | R/W | 0h | Unused |
5 | OE | R/W | 0h | Overrun error flag. This bit is set when a character is transferred into UxRXBUF before the previous character was read. OE is automatically reset when UxRXBUF is read, when SWRST = 1, or can be reset by software. 0b = No error 1b = Overrun error occurred |
4-0 | Unused | R/W | 0h | Unused |
USARTx Baud-Rate Control 0 Register
UxBR0 is shown in Figure 19-16 and described in Table 19-5.
Return to Table 19-1.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 |
rw | rw | rw | rw | rw | rw | rw | rw |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-0 | UxBR0 | R/W | 0h | The baud-rate generator uses the content of (UxBR1 + UxBR0) to set the baud rate. Unpredictable SPI operation occurs if UxBR < 2. |
USARTx Baud-Rate Control 1 Register
UxBR1 is shown in Figure 19-17 and described in Table 19-6.
Return to Table 19-1.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
215 | 214 | 213 | 212 | 211 | 210 | 29 | 28 |
rw | rw | rw | rw | rw | rw | rw | rw |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-0 | UxBR1 | R/W | 0h | The baud-rate generator uses the content of (UxBR1 + UxBR0) to set the baud rate. Unpredictable SPI operation occurs if UxBR < 2. |
USARTx Modulation Control Register
UxMCTL is shown in Figure 19-18 and described in Table 19-7.
Return to Table 19-1.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
m7 | m6 | m5 | m4 | m3 | m2 | m1 | m0 |
rw-0 | rw-0 | rw-0 | rw-0 | rw-0 | rw-0 | rw-0 | rw-0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-0 | UxMCTLx | R/W | 0h | The modulation control register is not used for SPI mode and should be set to 00h. |
USARTx Receive Buffer Register
UxRXBUF is shown in Figure 19-19 and described in Table 19-8.
Return to Table 19-1.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
UxRXBUFx | |||||||
r | r | r | r | r | r | r | r |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-0 | UxRXBUFx | R | 0h | The receive-data buffer is user accessible and contains the last received character from the receive shift register. Reading UxRXBUF resets the OE bit and URXIFGx flag. In 7-bit data mode, UxRXBUF is LSB justified and the MSB is always reset. |
USARTx Transmit Buffer Register
UxTXBUF is shown in Figure 19-20 and described in Table 19-9.
Return to Table 19-1.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
UxTXBUFx | |||||||
rw-0 | rw-0 | rw-0 | rw-0 | rw-0 | rw-0 | rw-0 | rw-0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-0 | UxTXBUFx | R/W | 0h | The transmit data buffer is user accessible and contains current data to be transmitted. When seven-bit character-length is used, the data should be MSB justified before being moved into UxTXBUF. Data is transmitted MSB first. Writing to UxTXBUF clears UTXIFGx. |
SFR Module Enable 1 Register
ME1 is shown in Figure 19-21 and described in Table 19-10.
Return to Table 19-1.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
USPIE0 | |||||||
rw-0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | This bit may be used by other modules. See the device-specific data sheet. | |||
6 | USPIE0 | R/W | 0h | USART0 SPI enable. This bit enables the SPI mode for USART0. 0b = Module not enabled 1b = Module enabled |
5-0 | These bits may be used by other modules. See the device-specific data sheet. |
SFR Module Enable 2 Register
ME2 is shown in Figure 19-22 and described in Table 19-11.
Return to Table 19-1.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
USPIE1 | |||||||
rw-0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | This bit may be used by other modules. See the device-specific data sheet. | |||
6 | USPIE1 | R/W | 0h | USART1 SPI enable. This bit enables the SPI mode for USART1. 0b = Module not enabled 1b = Module enabled |
5-0 | These bits may be used by other modules. See the device-specific data sheet. |
SFR Interrupt Enable 1 Register
IE1 is shown in Figure 19-23 and described in Table 19-12.
Return to Table 19-1.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
UTXIE0 | URXIE0 | ||||||
rw-0 | rw-0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | UTXIE0 | R/W | 0h | USART0 transmit interrupt enable. This bit enables the UTXIFG0 interrupt. 0b = Interrupt not enabled 1b = Interrupt enabled |
6 | URXIE0 | R/W | 0h | USART0 receive interrupt enable. This bit enables the URXIFG0 interrupt. 0b = Interrupt not enabled 1b = Interrupt enabled |
5-0 | These bits may be used by other modules. See the device-specific data sheet. |
SFR Interrupt Enable 2 Register
IE2 is shown in Figure 19-24 and described in Table 19-13.
Return to Table 19-1.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
UTXIE1 | URXIE1 | ||||||
rw-0 | rw-0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-6 | These bits may be used by other modules. See the device-specific data sheet. | |||
5 | UTXIE0 | R/W | 0h | USART1 transmit interrupt enable. This bit enables the UTXIFG1 interrupt. 0b = Interrupt not enabled 1b = Interrupt enabled |
4 | URXIE0 | R/W | 0h | USART1 receive interrupt enable. This bit enables the URXIFG1 interrupt. 0b = Interrupt not enabled 1b = Interrupt enabled |
3-0 | These bits may be used by other modules. See the device-specific data sheet. |
SFR Interrupt Flag 1 Register
IFG1 is shown in Figure 19-25 and described in Table 19-14.
Return to Table 19-1.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
UTXIFG0 | URXIFG0 | ||||||
rw-1 | rw-0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | UTXIFG0 | R/W | 1h | USART0 transmit interrupt flag. UTXIFG0 is set when U0TXBUF is empty. 0b = No interrupt pending 1b = Interrupt pending |
6 | URXIFG0 | R/W | 0h | USART0 receive interrupt flag. URXIFG0 is set when U0RXBUF has received a complete character. 0b = No interrupt pending 1b = Interrupt pending |
5-0 | These bits may be used by other modules. See the device-specific data sheet. |
SFR Interrupt Flag 2 Register
IFG2 is shown in Figure 19-26 and described in Table 19-15.
Return to Table 19-1.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
UTXIFG1 | URXIFG1 | ||||||
rw-1 | rw-0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-6 | These bits may be used by other modules. See the device-specific data sheet. | |||
5 | UTXIFG1 | R/W | 1h | USART1 transmit interrupt flag. UTXIFG1 is set when U1TXBUF is empty. 0b = No interrupt pending 1b = Interrupt pending |
4 | URXIFG1 | R/W | 0h | USART1 receive interrupt flag. URXIFG1 is set when U1RXBUF has received a complete character. 0b = No interrupt pending 1b = Interrupt pending |
3-0 | These bits may be used by other modules. See the device-specific data sheet. |