SLAU144K December 2004 – August 2022 MSP430AFE221 , MSP430AFE222 , MSP430AFE223 , MSP430AFE231 , MSP430AFE232 , MSP430AFE233 , MSP430AFE251 , MSP430AFE252 , MSP430AFE253 , MSP430F2001 , MSP430F2002 , MSP430F2003 , MSP430F2011 , MSP430F2012 , MSP430F2013 , MSP430F2101 , MSP430F2111 , MSP430F2112 , MSP430F2121 , MSP430F2122 , MSP430F2131 , MSP430F2132 , MSP430F2132-EP , MSP430F2232 , MSP430F2234 , MSP430F2252 , MSP430F2252-Q1 , MSP430F2254 , MSP430F2272 , MSP430F2272-Q1 , MSP430F2274 , MSP430F2274-EP , MSP430F233 , MSP430F2330 , MSP430F235 , MSP430F2350 , MSP430F2370 , MSP430F2410 , MSP430F2416 , MSP430F2417 , MSP430F2418 , MSP430F2419 , MSP430F247 , MSP430F2471 , MSP430F248 , MSP430F2481 , MSP430F249 , MSP430F2491 , MSP430F2616 , MSP430F2617 , MSP430F2618 , MSP430F2619 , MSP430G2001 , MSP430G2101 , MSP430G2102 , MSP430G2111 , MSP430G2112 , MSP430G2121 , MSP430G2131 , MSP430G2132 , MSP430G2152 , MSP430G2153 , MSP430G2201 , MSP430G2201-Q1 , MSP430G2202 , MSP430G2203 , MSP430G2210 , MSP430G2211 , MSP430G2212 , MSP430G2213 , MSP430G2221 , MSP430G2230 , MSP430G2231 , MSP430G2231-Q1 , MSP430G2232 , MSP430G2233 , MSP430G2252 , MSP430G2253 , MSP430G2302 , MSP430G2303 , MSP430G2312 , MSP430G2313 , MSP430G2332 , MSP430G2333 , MSP430G2352 , MSP430G2353 , MSP430G2402 , MSP430G2403 , MSP430G2412 , MSP430G2413 , MSP430G2432 , MSP430G2433 , MSP430G2444 , MSP430G2452 , MSP430G2453 , MSP430G2513 , MSP430G2533 , MSP430G2544 , MSP430G2553 , MSP430G2744 , MSP430G2755 , MSP430G2855 , MSP430G2955 , MSP430TCH5E
Table 18-3 lists the memory-mapped registers for USART0 and USART1 in UART mode.
Address | Acronym | Register Name | Type | Reset | Section |
---|---|---|---|---|---|
70h | U0CTL | USART0 control | Read/write | 01h with PUC | Section 18.4.1 |
71h | U0TCTL | USART0 transmit control | Read/write | 01h with PUC | Section 18.4.2 |
72h | U0RCTL | USART0 receive control | Read/write | 00h with PUC | Section 18.4.3 |
73h | U0MCTL | USART0 modulation control | Read/write | Unchanged | Section 18.4.4 |
74h | U0BR0 | USART0 baud-rate control 0 | Read/write | Unchanged | Section 18.4.5 |
75h | U0BR1 | USART0 baud-rate control 1 | Read/write | Unchanged | Section 18.4.5 |
76h | U0RXBUF | USART0 receive buffer | Read | Unchanged | Section 18.4.7 |
77h | U0TXBUF | USART0 transmit buffer | Read/write | Unchanged | Section 18.4.8 |
0h | IE1 | SFR interrupt enable 1 | Read/write | 00h with PUC | Section 18.4.9 |
2h | IFG1 | SFR interrupt flag 1 | Read/write | 82h with PUC | Section 18.4.11 |
78h | U1CTL | USART1 control | Read/write | 01h with PUC | Section 18.4.1 |
79h | U1TCTL | USART1 transmit control | Read/write | 01h with PUC | Section 18.4.2 |
7Ah | U1RCTL | USART1 receive control | Read/write | 00h with PUC | Section 18.4.3 |
7Bh | U1MCTL | USART1 modulation control | Read/write | Unchanged | Section 18.4.4 |
7Ch | U1BR0 | USART1 baud-rate control 0 | Read/write | Unchanged | Section 18.4.5 |
7Dh | U1BR1 | USART1 baud-rate control 1 | Read/write | Unchanged | Section 18.4.5 |
7Eh | U1RXBUF | USART1 receive buffer | Read | Unchanged | Section 18.4.7 |
7Fh | U1TXBUF | USART1 transmit buffer | Read/write | Unchanged | Section 18.4.8 |
1h | IE2 | SFR interrupt enable 2 | Read/write | 00h with PUC | Section 18.4.10 |
3h | IFG2 | SFR interrupt flag 2 | Read/write | 20h with PUC | Section 18.4.12 |
Modifying SFR bits
To avoid modifying control bits of other modules, TI recommends setting or clearing the IEx and IFGx bits using BIS.B or BIC.B instructions, rather than MOV.B or CLR.B instructions.
USARTx Control Register
UxCTL is shown in Figure 18-14 and described in Table 18-4.
Return to Table 18-3.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PENA | PEV | SPB | CHAR | LISTEN | SYNC | MM | SWRST |
rw-0 | rw-0 | rw-0 | rw-0 | rw-0 | rw-0 | rw-0 | rw-1 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | PENA | R/W | 0h | Parity enable 0b = Parity disabled 1b = Parity enabled. Parity bit is generated (UTXDx) and expected (URXDx). In address-bit multiprocessor mode, the address bit is included in the parity calculation. |
6 | PEV | R/W | 0h | Parity select. PEV is not used when parity is disabled. 0b = Odd parity 1b = Even parity |
5 | SPB | R/W | 0h | Stop bit select. Number of stop bits transmitted. The receiver always checks for one stop bit. 0b = One stop bit 1b = Two stop bits |
4 | CHAR | R/W | 0h | Character length. Selects 7-bit or 8-bit character length. 0b = 7-bit data 1b = 8-bit data |
3 | LISTEN | R/W | 0h | Listen enable. The LISTEN bit selects the loopback mode 0b = Disabled 1b = Enabled. UTXDx is internally fed back to the receiver. |
2 | SYNC | R/W | 0h | Synchronous mode enable 0b = UART mode 1b = SPI mode |
1 | MM | R/W | 0h | Multiprocessor mode select 0b = Idle-line multiprocessor protocol 1b = Address-bit multiprocessor protocol |
0 | SWRST | R/W | 1h | Software reset enable 0b = Disabled. USART reset released for operation. 1b = Enabled. USART logic held in reset state. |
USARTx Transmit Control Register
UxTCTL is shown in Figure 18-15 and described in Table 18-5.
Return to Table 18-3.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Unused | CKPL | SSELx | URXSE | TXWAKE | Unused | TXEPT | |
rw-0 | rw-0 | rw-0 | rw-0 | rw-0 | rw-0 | rw-0 | rw-1 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | Unused | R/W | 0h | Unused |
6 | CKPL | R/W | 0h | Clock polarity select 0b = UCLKI = UCLK 1b = UCLKI = Inverted UCLK |
5-4 | SSELx | R/W | 0h | Source select. These bits select the BRCLK source clock. 00b = UCLKI 01b = ACLK 10b = SMCLK 11b = SMCLK |
3 | URXSE | R/W | 0h | UART receive start-edge. The bit enables the UART receive start-edge feature. 0b = Disabled 1b = Enabled |
2 | TXWAKE | R/W | 0h | Transmitter wake 0b = Next frame transmitted is data 1b = Next frame transmitted is an address |
1 | Unused | R/W | 0h | Unused |
0 | TXEPT | R/W | 1h | Transmitter empty flag. 0b = UART is transmitting data and/or data is waiting in UxTXBUF 1b = Transmitter shift register and UxTXBUF are empty or SWRST = 1 |
USARTx Receive Control Register
UxRCTL is shown in Figure 18-16 and described in Table 18-6.
Return to Table 18-3.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FE | PE | OE | BRK | URXEIE | URXWIE | RXWAKE | RXERR |
rw-0 | rw-0 | rw-0 | rw-0 | rw-0 | rw-0 | rw-0 | rw-0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | FE | R/W | 0h | Framing error flag. 0b = No error 1b = Character received with low stop bit |
6 | PE | R/W | 0h | Parity error flag. When PENA = 0, PE is read as 0. 0b = No error 1b = Character received with parity error |
5 | OE | R/W | 0h | Overrun error flag. This bit is set when a character is transferred into UxRXBUF before the previous character was read. 0b = No error 1b = Overrun error occurred |
4 | BRK | R/W | 0h | Break detect flag 0b = No break condition 1b = Break condition occurred |
3 | URXEIE | R/W | 0h | Receive erroneous-character interrupt-enable 0b = Erroneous characters rejected and URXIFGx is not set 1b = Erroneous characters received set URXIFGx |
2 | URXWIE | R/W | 0h | Receive wake-up interrupt-enable. This bit enables URXIFGx to be set when an address character is received. When URXEIE = 0, an address character does not set URXIFGx if it is received with errors. 0b = All received characters set URXIFGx 1b = Only received address characters set URXIFGx |
1 | RXWAKE | R/W | 0h | Receive wake-up flag 0b = Received character is data 1b = Received character is an address |
0 | RXERR | R/W | 0h | Receive error flag. This bit indicates a character was received with errors. When RXERR = 1, one or more error flags (FE, PE, OE, BRK) is also set. RXERR is cleared when UxRXBUF is read. 0b = No receive errors detected 1b = Receive error detected |
USARTx Modulation Control Register
UxMCTL is shown in Figure 18-17 and described in Table 18-7.
Return to Table 18-3.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
m7 | m6 | m5 | m4 | m3 | m2 | m1 | m0 |
rw | rw | rw | rw | rw | rw | rw | rw |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-0 | UxMCTLx | R/W | Unchanged | Modulation bits. These bits select the modulation for BRCLK. |
USARTx Baud-Rate Control 0 Register
UxBR0 is shown in Figure 18-18 and described in Table 18-8.
Return to Table 18-3.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 |
rw | rw | rw | rw | rw | rw | rw | rw |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-0 | UxBRx | R/W | Unchanged | The valid baud-rate control range is 3 ≤ UxBR ≤ 0FFFFh, where UxBR = (UxBR1 + UxBR0). Unpredictable receive and transmit timing occurs if UxBR < 3. |
USARTx Baud-Rate Control 1 Register
UxBR1 is shown in Figure 18-18 and described in Table 18-8.
Return to Table 18-3.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
215 | 214 | 213 | 212 | 211 | 210 | 29 | 28 |
rw | rw | rw | rw | rw | rw | rw | rw |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-0 | UxBRx | R/W | Unchanged | The valid baud-rate control range is 3 ≤ UxBR ≤ 0FFFFh, where UxBR = (UxBR1 + UxBR0). Unpredictable receive and transmit timing occurs if UxBR < 3. |
USARTx Receive Buffer Register
UxRXBUF is shown in Figure 18-20 and described in Table 18-10.
Return to Table 18-3.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
UxRXBUFx | |||||||
r | r | r | r | r | r | r | r |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-0 | UxRXBUFx | R | Unchanged | The receive-data buffer is user accessible and contains the last received character from the receive shift register. Reading UxRXBUF resets the OE bit and URXIFGx flag. In 7-bit data mode, UxRXBUF is LSB justified and the MSB is always reset. |
USARTx Transmit Buffer Register
UxTXBUF is shown in Figure 18-21 and described in Table 18-11.
Return to Table 18-3.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
UxTXBUFx | |||||||
rw | rw | rw | rw | rw | rw | rw | rw |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-0 | UxTXBUFx | R/W | Unchanged | The transmit data buffer is user accessible and holds the data waiting to be moved into the transmit shift register and transmitted on UTXDx. Writing to the transmit data buffer clears UTXIFGx. The MSB of UxTXBUF is not used for 7-bit data and is reset. |
SFR Interrupt Enable 1 Register
IE1 is shown in Figure 18-22 and described in Table 18-12.
Return to Table 18-3.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
UTXIE0 | URXIE0 | ||||||
rw-0 | rw-0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | UTXIE0 | R/W | 0h | USART0 transmit interrupt enable. This bit enables the UTXIFG0 interrupt. 0b = Interrupt not enabled 1b = Interrupt enabled |
6 | URXIE0 | R/W | 0h | USART0 receive interrupt enable. This bit enables the URXIFG0 interrupt. 0b = Interrupt not enabled 1b = Interrupt enabled |
5-0 | These bits may be used by other modules. See the device-specific data sheet. |
SFR Interrupt Enable 2 Register
IE2 is shown in Figure 18-23 and described in Table 18-13.
Return to Table 18-3.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
UTXIE1 | URXIE1 | ||||||
rw-0 | rw-0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-6 | These bits may be used by other modules. See the device-specific data sheet. | |||
5 | UTXIE1 | R/W | 0h | USART1 transmit interrupt enable. This bit enables the UTXIFG1 interrupt. 0b = Interrupt not enabled 1b = Interrupt enabled |
4 | URXIE1 | R/W | 0h | USART1 receive interrupt enable. This bit enables the URXIFG1 interrupt. 0b = Interrupt not enabled 1b = Interrupt enabled |
3-0 | These bits may be used by other modules. See the device-specific data sheet. |
SFR Interrupt Flag 1 Register
IFG1 is shown in Figure 18-24 and described in Table 18-14.
Return to Table 18-3.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
UTXIFG0 | URXIFG0 | ||||||
rw-1 | rw-0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | UTXIFG0 | R/W | 1h | USART0 transmit interrupt flag. UTXIFG0 is set when U0TXBUF is empty. 0b = No interrupt pending 1b = Interrupt pending |
6 | URXIFG0 | R/W | 0h | USART0 receive interrupt flag. URXIFG0 is set when U0RXBUF has received a complete character. 0b = No interrupt pending 1b = Interrupt pending |
5-0 | These bits may be used by other modules. See the device-specific data sheet. |
SFR Interrupt Flag 2 Register
IFG2 is shown in Figure 18-25 and described in Table 18-15.
Return to Table 18-3.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
UTXIFG1 | URXIFG1 | ||||||
rw-1 | rw-0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-6 | These bits may be used by other modules. See the device-specific data sheet. | |||
5 | UTXIFG1 | R/W | 1h | USART1 transmit interrupt flag. UTXIFG1 is set when U1TXBUF is empty. 0b = No interrupt pending 1b = Interrupt pending |
4 | URXIFG1 | R/W | 0h | USART1 receive interrupt flag. URXIFG1 is set when U1RXBUF has received a complete character. 0b = No interrupt pending 1b = Interrupt pending |
3-0 | These bits may be used by other modules. See the device-specific data sheet. |