SLAU144K December 2004 – August 2022 MSP430AFE221 , MSP430AFE222 , MSP430AFE223 , MSP430AFE231 , MSP430AFE232 , MSP430AFE233 , MSP430AFE251 , MSP430AFE252 , MSP430AFE253 , MSP430F2001 , MSP430F2002 , MSP430F2003 , MSP430F2011 , MSP430F2012 , MSP430F2013 , MSP430F2101 , MSP430F2111 , MSP430F2112 , MSP430F2121 , MSP430F2122 , MSP430F2131 , MSP430F2132 , MSP430F2132-EP , MSP430F2232 , MSP430F2234 , MSP430F2252 , MSP430F2252-Q1 , MSP430F2254 , MSP430F2272 , MSP430F2272-Q1 , MSP430F2274 , MSP430F2274-EP , MSP430F233 , MSP430F2330 , MSP430F235 , MSP430F2350 , MSP430F2370 , MSP430F2410 , MSP430F2416 , MSP430F2417 , MSP430F2418 , MSP430F2419 , MSP430F247 , MSP430F2471 , MSP430F248 , MSP430F2481 , MSP430F249 , MSP430F2491 , MSP430F2616 , MSP430F2617 , MSP430F2618 , MSP430F2619 , MSP430G2001 , MSP430G2101 , MSP430G2102 , MSP430G2111 , MSP430G2112 , MSP430G2121 , MSP430G2131 , MSP430G2132 , MSP430G2152 , MSP430G2153 , MSP430G2201 , MSP430G2201-Q1 , MSP430G2202 , MSP430G2203 , MSP430G2210 , MSP430G2211 , MSP430G2212 , MSP430G2213 , MSP430G2221 , MSP430G2230 , MSP430G2231 , MSP430G2231-Q1 , MSP430G2232 , MSP430G2233 , MSP430G2252 , MSP430G2253 , MSP430G2302 , MSP430G2303 , MSP430G2312 , MSP430G2313 , MSP430G2332 , MSP430G2333 , MSP430G2352 , MSP430G2353 , MSP430G2402 , MSP430G2403 , MSP430G2412 , MSP430G2413 , MSP430G2432 , MSP430G2433 , MSP430G2444 , MSP430G2452 , MSP430G2453 , MSP430G2513 , MSP430G2533 , MSP430G2544 , MSP430G2553 , MSP430G2744 , MSP430G2755 , MSP430G2855 , MSP430G2955 , MSP430TCH5E
Table 13-5 lists the memory-mapped registers for the Timer_B.
Address | Acronym | Register Name | Type | Reset | Section |
---|---|---|---|---|---|
180h | TBCTL | Timer_B control | Read/write | 00h with POR | Section 13.4.1 |
190h | TBR | Timer_B counter | Read/write | 00h with POR | Section 13.4.2 |
182h | TBCCTL0 | Timer_B capture/compare control 0 | Read/write | 00h with POR | Section 13.4.3 |
192h | TBCCR0 | Timer_B capture/compare 0 | Read/write | 00h with POR | Section 13.4.4 |
184h | TBCCTL1 | Timer_B capture/compare control 1 | Read/write | 00h with POR | Section 13.4.3 |
194h | TBCCR1 | Timer_B capture/compare 1 | Read/write | 00h with POR | Section 13.4.4 |
186h | TBCCTL2 | Timer_B capture/compare control 2 | Read/write | 00h with POR | Section 13.4.3 |
196h | TBCCR2 | Timer_B capture/compare 2 | Read/write | 00h with POR | Section 13.4.4 |
188h | TBCCTL3 | Timer_B capture/compare control 3 | Read/write | 00h with POR | Section 13.4.3 |
198h | TBCCR3 | Timer_B capture/compare 3 | Read/write | 00h with POR | Section 13.4.4 |
18Ah | TBCCTL4 | Timer_B capture/compare control 4 | Read/write | 00h with POR | Section 13.4.3 |
19Ah | TBCCR4 | Timer_B capture/compare 4 | Read/write | 00h with POR | Section 13.4.4 |
18Ch | TBCCTL5 | Timer_B capture/compare control 5 | Read/write | 00h with POR | Section 13.4.3 |
19Ch | TBCCR5 | Timer_B capture/compare 5 | Read/write | 00h with POR | Section 13.4.4 |
18Eh | TBCCTL6 | Timer_B capture/compare control 6 | Read/write | 00h with POR | Section 13.4.3 |
19Eh | TBCCR6 | Timer_B capture/compare 6 | Read/write | 00h with POR | Section 13.4.4 |
11Eh | TBIV | Timer_B interrupt vector | Read | 00h with POR | Section 13.4.5 |
Timer_B Control Register
TBCTL is shown in Figure 13-16 and described in Table 13-6.
Return to Table 13-5.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
Unused | TBCLGRPx | CNTLx | Unused | TBSSELx | |||
rw-(0) | rw-(0) | rw-(0) | rw-(0) | rw-(0) | rw-(0) | rw-(0) | rw-(0) |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
IDx | MCx | Unused | TBCLR | TBIE | TBIFG | ||
rw-(0) | rw-(0) | rw-(0) | rw-(0) | rw-(0) | w-(0) | rw-(0) | rw-(0) |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15 | Unused | R/W | 0h | |
14-13 | TBCLGRP | R/W | 0h | TBCLx group 00b = Each TBCLx latch loads independently 01b = TBCL1+TBCL2 (TBCCR1 CLLDx bits control the update) 10b = TBCL1+TBCL2+TBCL3 (TBCCR1 CLLDx bits control the update) 11b = TBCL0+TBCL1+TBCL2+TBCL3+TBCL4+TBCL5+TBCL6 (TBCCR1 CLLDx bits control the update) |
12-11 | CNTLx | R/W | 0h | Counter length 00b = 16 bit, TBR(max) = 0FFFFh 01b = 12 bit, TBR(max) = 0FFFh 10b = 10 bit, TBR(max) = 03FFh 11b = 8 bit, TBR(max) = 0FFh |
10 | Unused | R/W | 0h | |
9-8 | TBSSELx | R/W | 0h | Timer_B clock source select. 00b = TBCLK 01b = ACLK 10b = SMCLK 11b = INCLK (INCLK is device-specific and is often assigned to the inverted TBCLK) (see the device-specific data sheet) |
7-6 | IDx | R/W | 0h | Input divider. These bits select the divider for the input clock. 00b = /1 01b = /2 10b = /4 11b = /8 |
5-4 | MCx | R/W | 0h | Mode control. Set MCx = 00b when Timer_B is not in use to conserve power. 00b = Stop mode: the timer is halted 01b = Up mode: the timer counts up to TBCL0 10b = Continuous mode: the timer counts up to the value set by CNTLx 11b = Up/down mode: the timer counts up to TBCL0 and down to 0000h |
3 | Unused | R/W | 0h | |
2 | TBCLR | W | 0h | Timer_B clear. Setting this bit resets TBR, the clock divider, and the count direction. The TBCLR bit is automatically reset and is always read as zero. |
1 | TBIE | R/W | 0h | Timer_B interrupt enable. This bit enables the TBIFG interrupt request. 0b = Interrupt disabled 1b = Interrupt enabled |
0 | TBIFG | R/W | 0h | Timer_B interrupt flag. 0b = No interrupt pending 1b = Interrupt pending |
Timer_B Counter Register
TBR is shown in Figure 13-17 and described in Table 13-7.
Return to Table 13-5.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
TBRx | |||||||
rw-(0) | rw-(0) | rw-(0) | rw-(0) | rw-(0) | rw-(0) | rw-(0) | rw-(0) |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TBRx | |||||||
rw-(0) | rw-(0) | rw-(0) | rw-(0) | rw-(0) | rw-(0) | rw-(0) | rw-(0) |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-0 | TBRx | R/W | 0h | Timer_B register. The TBR register is the count of Timer_B. |
Timer_B Capture/Compare Control x Register
TBCCTLx is shown in Figure 13-18 and described in Table 13-8.
Return to Table 13-5.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
CMx | CCISx | SCS | CLLDx | CAP | |||
rw-(0) | rw-(0) | rw-(0) | rw-(0) | rw-(0) | rw-(0) | r-(0) | rw-(0) |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
OUTMODx | CCIE | CCI | OUT | COV | CCIFG | ||
rw-(0) | rw-(0) | rw-(0) | rw-(0) | r-(0) | rw-(0) | rw-(0) | rw-(0) |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-14 | CMx | R/W | 0h | Capture mode 00b = No capture 01b = Capture on rising edge 10b = Capture on falling edge 11b = Capture on both rising and falling edges |
13-12 | CCISx | R/W | 0h | Capture/compare input select. These bits select the TBCCRx input signal. See the device-specific data sheet for specific signal connections. 00b = CCIxA 01b = CCIxB 10b = GND 11b = VCC |
11 | SCS | R/W | 0h | Synchronize capture source. This bit is used to synchronize the capture input signal with the timer clock. 0b = Asynchronous capture 1b = Synchronous capture |
10-9 | CLLDx | R/W | 0h | Compare latch load. These bits select the compare latch load event. 00b = TBCLx loads on write to TBCCRx 01b = TBCLx loads when TBR counts to 0 10b = TBCLx loads when TBR counts to 0 (up or continuous mode) 11b = TBCLx loads when TBR counts to TBCLx |
8 | CAP | R/W | 0h | Capture mode 0b = Compare mode 1b = Capture mode |
7-5 | OUTMODx | R/W | 0h | Output mode. Modes 2, 3, 6, and 7 are not useful for TBCL0 because EQUx = EQU0. 000b = OUT bit value 001b = Set 010b = Toggle/reset 011b = Set/reset 100b = Toggle 101b = Reset 110b = Toggle/set 111b = Reset/set |
4 | CCIE | R/W | 0h | Capture/compare interrupt enable. This bit enables the interrupt request of the corresponding CCIFG flag. 0b = Interrupt disabled 1b = Interrupt enabled |
3 | CCI | R | 0h | Capture/compare input. The selected input signal can be read by this bit. |
2 | OUT | R/W | 0h | Output. For output mode 0, this bit directly controls the state of the output. 0b = Output low 1b = Output high |
1 | COV | R/W | 0h | Capture overflow. This bit indicates a capture overflow occurred. COV must be reset with software. 0b = No capture overflow occurred 1b = Capture overflow occurred |
0 | CCIFG | R/W | 0h | Capture/compare interrupt flag 0b = No interrupt pending 1b = Interrupt pending |
Timer_B Capture/Compare x Register
TBCCRx is shown in Figure 13-19 and described in Table 13-9.
Return to Table 13-5.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
TBCCRx | |||||||
rw-(0) | rw-(0) | rw-(0) | rw-(0) | rw-(0) | rw-(0) | rw-(0) | rw-(0) |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TBCCRx | |||||||
rw-(0) | rw-(0) | rw-(0) | rw-(0) | rw-(0) | rw-(0) | rw-(0) | rw-(0) |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-0 | TBCCRx | R/W | 0h | Timer_B capture/compare register. Compare mode: Compare data is written to each TBCCRx and automatically transferred to TBCLx. TBCLx holds the data for the comparison to the timer value in the Timer_B Register, TBR. Capture mode: The Timer_B Register, TBR, is copied into the TBCCRx register when a capture is performed. |
TBIV is shown in Figure 13-20 and described in Table 13-10.
Return to Table 13-5.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
TBIVx | |||||||
r0 | r0 | r0 | r0 | r0 | r0 | r0 | r0 |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TBIVx | |||||||
r0 | r0 | r0 | r0 | r-(0) | r-(0) | r-(0) | r0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-0 | TBIVx | R | 0h | Timer_B interrupt vector value. See Table 13-11 for values. |
TBIV Contents | Interrupt Source | Interrupt Flag | Interrupt Priority |
---|---|---|---|
00h | No interrupt pending | – | |
02h | Capture/compare 1 | TBCCR1 CCIFG | Highest |
04h | Capture/compare 2 | TBCCR2 CCIFG | |
06h | Capture/compare 3#SLAU144TB7804 | TBCCR3 CCIFG | |
08h | Capture/compare 4#SLAU144TB7804 | TBCCR4 CCIFG | |
0Ah | Capture/compare 5#SLAU144TB7804 | TBCCR5 CCIFG | |
0Ch | Capture/compare 6#SLAU144TB7804 | TBCCR6 CCIFG | |
0Eh | Timer overflow | TBIFG | Lowest |