SLAU144K December 2004 – August 2022 MSP430AFE221 , MSP430AFE222 , MSP430AFE223 , MSP430AFE231 , MSP430AFE232 , MSP430AFE233 , MSP430AFE251 , MSP430AFE252 , MSP430AFE253 , MSP430F2001 , MSP430F2002 , MSP430F2003 , MSP430F2011 , MSP430F2012 , MSP430F2013 , MSP430F2101 , MSP430F2111 , MSP430F2112 , MSP430F2121 , MSP430F2122 , MSP430F2131 , MSP430F2132 , MSP430F2132-EP , MSP430F2232 , MSP430F2234 , MSP430F2252 , MSP430F2252-Q1 , MSP430F2254 , MSP430F2272 , MSP430F2272-Q1 , MSP430F2274 , MSP430F2274-EP , MSP430F233 , MSP430F2330 , MSP430F235 , MSP430F2350 , MSP430F2370 , MSP430F2410 , MSP430F2416 , MSP430F2417 , MSP430F2418 , MSP430F2419 , MSP430F247 , MSP430F2471 , MSP430F248 , MSP430F2481 , MSP430F249 , MSP430F2491 , MSP430F2616 , MSP430F2617 , MSP430F2618 , MSP430F2619 , MSP430G2001 , MSP430G2101 , MSP430G2102 , MSP430G2111 , MSP430G2112 , MSP430G2121 , MSP430G2131 , MSP430G2132 , MSP430G2152 , MSP430G2153 , MSP430G2201 , MSP430G2201-Q1 , MSP430G2202 , MSP430G2203 , MSP430G2210 , MSP430G2211 , MSP430G2212 , MSP430G2213 , MSP430G2221 , MSP430G2230 , MSP430G2231 , MSP430G2231-Q1 , MSP430G2232 , MSP430G2233 , MSP430G2252 , MSP430G2253 , MSP430G2302 , MSP430G2303 , MSP430G2312 , MSP430G2313 , MSP430G2332 , MSP430G2333 , MSP430G2352 , MSP430G2353 , MSP430G2402 , MSP430G2403 , MSP430G2412 , MSP430G2413 , MSP430G2432 , MSP430G2433 , MSP430G2444 , MSP430G2452 , MSP430G2453 , MSP430G2513 , MSP430G2533 , MSP430G2544 , MSP430G2553 , MSP430G2744 , MSP430G2755 , MSP430G2855 , MSP430G2955 , MSP430TCH5E
Table 17-2 lists the memory-mapped registers for the USCI_Bx in I2C mode.
Address | Acronym | Register Name | Type | Reset | Section |
---|---|---|---|---|---|
68h | UCB0CTL0 | USCI_B0 control 0 | Read/write | 01h with PUC | Section 17.5.1 |
69h | UCB0CTL1 | USCI_B0 control 1 | Read/write | 01h with PUC | Section 17.5.2 |
6Ah | UCB0BR0 | USCI_B0 bit rate control 0 | Read/write | 00h with PUC | Section 17.5.3 |
6Bh | UCB0BR1 | USCI_B0 bit rate control 1 | Read/write | 00h with PUC | Section 17.5.3 |
6Ch | UCB0I2CIE | USCI_B0 I2C interrupt enable | Read/write | 00h with PUC | Section 17.5.10 |
6Dh | UCB0STAT | USCI_B0 status | Read/write | 00h with PUC | Section 17.5.5 |
6Eh | UCB0RXBUF | USCI_B0 receive buffer | Read | 00h with PUC | Section 17.5.6 |
6Fh | UCB0TXBUF | USCI_B0 transmit buffer | Read/write | 00h with PUC | Section 17.5.7 |
118h | UCB0I2COA | USCI_B0 I2C own address | Read/write | 00h with PUC | Section 17.5.8 |
11Ah | UCB0I2CSA | USCI_B0 I2C slave address | Read/write | 00h with PUC | Section 17.5.9 |
1h | IE2 | SFR interrupt enable 2 | Read/write | 00h with PUC | Section 17.5.11 |
3h | IFG2 | SFR interrupt flag 2 | Read/write | 0Ah with PUC | Section 17.5.12 |
0D8h | UCB1CTL0 | USCI_B1 control 0 | Read/write | 01h with PUC | Section 17.5.1 |
0D9h | UCB1CTL1 | USCI_B1 control 1 | Read/write | 01h with PUC | Section 17.5.1 |
0DAh | UCB1BR0 | USCI_B1 bit rate control 0 | Read/write | 00h with PUC | Section 17.5.3 |
0DBh | UCB1BR1 | USCI_B1 bit rate control 1 | Read/write | 00h with PUC | Section 17.5.3 |
0DCh | UCB1I2CIE | USCI_B1 I2C interrupt enable | Read/write | 00h with PUC | Section 17.5.10 |
0DDh | UCB1STAT | USCI_B1 status | Read/write | 00h with PUC | Section 17.5.5 |
0DEh | UCB1RXBUF | USCI_B1 receive buffer | Read | 00h with PUC | Section 17.5.6 |
0DFh | UCB1TXBUF | USCI_B1 transmit buffer | Read/write | 00h with PUC | Section 17.5.7 |
17Ch | UCB1I2COA | USCI_B1 I2C own address | Read/write | 00h with PUC | Section 17.5.8 |
17Eh | UCB1I2CSA | USCI_B1 I2C slave address | Read/write | 00h with PUC | Section 17.5.9 |
6h | UC1IE | USCI_A1/B1 interrupt enable | Read/write | 00h with PUC | Section 17.5.13 |
7h | UC1IFG | USCI_A1/B1 interrupt flag | Read/write | 0Ah with PUC | Section 17.5.14 |
Modifying SFR bits
To avoid modifying control bits of other modules, TI recommends setting or clearing the IEx and IFGx bits using BIS.B or BIC.B instructions, rather than MOV.B or CLR.B instructions.
USCI_Bx Control 0 Register
UCBxCTL0 is shown in Figure 17-17 and described in Table 17-3.
Return to Table 17-2.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
UCA10 | UCSLA10 | UCMM | Unused | UCMST | UCMODEx=11 | UCSYNC=1 | |
rw-0 | rw-0 | rw-0 | rw-0 | rw-0 | rw-0 | rw-0 | r-1 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | UCA10 | R/W | 0h | Own addressing mode select 0b = Own address is a 7-bit address 1b = Own address is a 10-bit address |
6 | UCSLA10 | R/W | 0h | Slave addressing mode select 0b = Address slave with 7-bit address 1b = Address slave with 10-bit address |
5 | UCMM | R/W | 0h | Multi-master environment select 0b = Single master environment. There is no other master in the system. The address compare unit is disabled. 1b = Multi-master environment |
4 | Unused | R/W | 0h | Unused |
3 | UCMST | R/W | 0h | Master mode select. When a master loses arbitration in a multi-master environment (UCMM = 1) the UCMST bit is automatically cleared and the module acts as slave. 0b = Slave mode 1b = Master mode |
2-1 | UCMODEx | R/W | 0h | USCI Mode. The UCMODEx bits select the synchronous mode when UCSYNC = 1. 00b = 3-pin SPI 01b = 4-pin SPI (master/slave enabled if STE = 1) 10b = 4-pin SPI (master/slave enabled if STE = 0) 11b = I2C mode |
0 | UCSYNC | R | 1h | Synchronous mode enable 0b = Asynchronous mode 1b = Synchronous mode |
USCI_Bx Control 1 Register
UCBxCTL1 is shown in Figure 17-18 and described in Table 17-4.
Return to Table 17-2.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
UCSSELx | Unused | UCTR | UCTXNACK | UCTXSTP | UCTXSTT | UCSWRST | |
rw-0 | rw-0 | r0 | rw-0 | rw-0 | rw-0 | rw-0 | rw-1 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-6 | UCSSELx | R/W | 0h | USCI clock source select. These bits select the BRCLK source clock. 00b = UCLKI 01b = ACLK 10b = SMCLK 11b = SMCLK |
5 | Unused | R | 0h | Unused |
4 | UCTR | R/W | 0h | Transmitter or receiver 0b = Receiver 1b = Transmitter |
3 | UCTXNACK | R/W | 0h | Transmit a NACK. UCTXNACK is automatically cleared after a NACK is transmitted. 0b = Acknowledge normally 1b = Generate NACK |
2 | UCTXSTP | R/W | 0h | Transmit STOP condition in master mode. Ignored in slave mode. In master receiver mode, the STOP condition is preceded by a NACK. UCTXSTP is automatically cleared after STOP is generated. 0b = No STOP generated 1b = Generate STOP |
1 | UCTXSTT | R/W | 0h | Transmit START condition in master mode. Ignored in slave mode. In master receiver mode a repeated START condition is preceded by a NACK. UCTXSTT is automatically cleared after START condition and address information is transmitted. Ignored in slave mode. 0b = Do not generate START condition 1b = Generate START condition |
0 | UCSWRST | R/W | 1h | Software reset enable 0b = Disabled. USCI reset released for operation. 1b = Enabled. USCI logic held in reset state. |
USCI_Bx Bit-Rate Control 0 Register
UCBxBR0 is shown in Figure 17-19 and described in Table 17-5.
Return to Table 17-2.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
UCBRx (low byte) | |||||||
rw | rw | rw | rw | rw | rw | rw | rw |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-0 | UCBRx | R/W | 0h | Bit clock prescaler setting. The 16-bit value of (UCBxBR0 + UCBxBR1 × 256) forms the prescaler value. |
USCI_Bx Bit-Rate Control 1 Register
UCBxBR1 is shown in Figure 17-20 and described in Table 17-6.
Return to Table 17-2.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
UCBRx (high byte) | |||||||
rw | rw | rw | rw | rw | rw | rw | rw |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-0 | UCBRx | R/W | 0h | Bit clock prescaler setting. The 16-bit value of (UCBxBR0 + UCBxBR1 × 256) forms the prescaler value. |
USCI_Bx Status Register
UCBxSTAT is shown in Figure 17-21 and described in Table 17-7.
Return to Table 17-2.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Unused | UCSCLLOW | UCGC | UCBBUSY | UCNACKIFG | UCSTPIFG | UCSTTIFG | UCALIFG |
rw-0 | r-0 | rw-0 | r-0 | rw-0 | rw-0 | rw-0 | rw-0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | Unused | R/W | 0h | Unused |
6 | UCSCLLOW | R | 0h | SCL low 0b = SCL is not held low 1b = SCL is held low |
5 | UCGC | R/W | 0h | General call address received. UCGC is automatically cleared when a START condition is received. 0b = No general call address received 1b = General call address received |
4 | UCBBUSY | R | 0h | Bus busy 0b = Bus inactive 1b = Bus busy |
3 | UCNACKIFG | R/W | 0h | Not-acknowledge received interrupt flag. UCNACKIFG is automatically cleared when a START condition is received. 0b = No interrupt pending 1b = Interrupt pending |
2 | UCSTPIFG | R/W | 0h | Stop condition interrupt flag. UCSTPIFG is automatically cleared when a START condition is received. 0b = No interrupt pending 1b = Interrupt pending |
1 | UCSTTIFG | R/W | 0h | Start condition interrupt flag. UCSTTIFG is automatically cleared if a STOP condition is received. 0b = No interrupt pending 1b = Interrupt pending |
0 | UCALIFG | R/W | 0h | Arbitration lost interrupt flag 0b = No interrupt pending 1b = Interrupt pending |
USCI_Bx Receive Buffer Register
UCBxRXBUF is shown in Figure 17-22 and described in Table 17-8.
Return to Table 17-2.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
UCRXBUFx | |||||||
r-0 | r-0 | r-0 | r-0 | r-0 | r-0 | r-0 | r-0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-0 | UCRXBUFx | R | 0h | The receive-data buffer is user accessible and contains the last received character from the receive shift register. Reading UCBxRXBUF resets UCBxRXIFG. |
USCI_Bx Transmit Buffer Register
UCBxTXBUF is shown in Figure 17-23 and described in Table 17-9.
Return to Table 17-2.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
UCTXBUFx | |||||||
rw-0 | rw-0 | rw-0 | rw-0 | rw-0 | rw-0 | rw-0 | rw-0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-0 | UCTXBUFx | R/W | 0h | The transmit data buffer is user accessible and holds the data waiting to be moved into the transmit shift register and transmitted. Writing to the transmit data buffer clears UCBxTXIFG. |
USCI_Bx I2C Own Address Register
UCBxI2COA is shown in Figure 17-24 and described in Table 17-10.
Return to Table 17-2.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
UCGCEN | Reserved | I2COAx | |||||
rw-0 | r-0 | r-0 | r-0 | r-0 | r-0 | rw-0 | rw-0 |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
I2COAx | |||||||
rw-0 | rw-0 | rw-0 | rw-0 | rw-0 | rw-0 | rw-0 | rw-0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15 | UCGCEN | R/W | 0h | General call response enable
0b = Do not respond to a general call 1b = Respond to a general call |
14-10 | Reserved | R | 0h | |
9-0 | I2COAx | R/W | 0h | I2C own address. The I2COAx bits contain the local address of the USCI_Bx I2C controller. The address is right-justified. In 7-bit addressing mode, bit 6 is the MSB, and bits 9-7 are ignored. In 10-bit addressing mode, bit 9 is the MSB. |
USCI_Bx I2C Slave Address Register
UCBxI2CSA is shown in Figure 17-25 and described in Table 17-11.
Return to Table 17-2.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
Reserved | I2CSAx | ||||||
r-0 | r-0 | r-0 | r-0 | r-0 | r-0 | rw-0 | rw-0 |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
I2CSAx | |||||||
rw-0 | rw-0 | rw-0 | rw-0 | rw-0 | rw-0 | rw-0 | rw-0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-10 | Reserved | R | 0h | |
9-0 | I2CSAx | R/W | 0h | I2C slave address. The I2CSAx bits contain the slave address of the external device to be addressed by the USCI_Bx module. It is only used in master mode. The address is right-justified. In 7-bit slave addressing mode, bit 6 is the MSB, and bits 9-7 are ignored. In 10-bit slave addressing mode, bit 9 is the MSB. |
USCI_Bx I2C Interrupt Enable Register
UCBxI2CIE is shown in Figure 17-26 and described in Table 17-12.
Return to Table 17-2.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Reserved | UCNACKIE | UCSTPIE | UCSTTIE | UCALIE | |||
rw-0 | rw-0 | rw-0 | rw-0 | rw-0 | rw-0 | rw-0 | rw-0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-4 | Reserved | R/W | 0h | |
3 | UCNACKIE | R/W | 0h | Not-acknowledge interrupt enable 0b = Interrupt disabled 1b = Interrupt enabled |
2 | UCSTPIE | R/W | 0h | Stop condition interrupt enable 0b = Interrupt disabled 1b = Interrupt enabled |
1 | UCSTTIE | R/W | 0h | Start condition interrupt enable 0b = Interrupt disabled 1b = Interrupt enabled |
0 | UCALIE | R/W | 0h | Arbitration lost interrupt enable 0b = Interrupt disabled 1b = Interrupt enabled |
SFR Interrupt Enable 2 Register
IE2 is shown in Figure 17-27 and described in Table 17-13.
Return to Table 17-2.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
UCB0TXIE | UCB0RXIE | ||||||
rw-0 | rw-0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-4 | These bits may be used by other modules (see the device-specific data sheet). | |||
3 | UCB0TXIE | R/W | 0h | USCI_B0 transmit interrupt enable 0b = Interrupt disabled 1b = Interrupt enabled |
2 | UCB0RXIE | R/W | 0h | USCI_B0 receive interrupt enable 0b = Interrupt disabled 1b = Interrupt enabled |
1-0 | These bits may be used by other modules (see the device-specific data sheet). |
SFR Interrupt Flag 2 Register
IFG2 is shown in Figure 17-28 and described in Table 17-14.
Return to Table 17-2.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
UCB0TXIFG | UCB0RXIFG | ||||||
rw-1 | rw-0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-4 | These bits may be used by other modules (see the device-specific data sheet). | |||
3 | UCB0TXIFG | R/W | 1h | USCI_B0 transmit interrupt flag. UCB0TXIFG is set when UCB0TXBUF is empty. 0b = No interrupt pending 1b = Interrupt pending |
2 | UCB0RXIFG | R/W | 0h | USCI_B0 receive interrupt flag. UCB0RXIFG is set when UCB0RXBUF has received a complete character. 0b = No interrupt pending 1b = Interrupt pending |
1-0 | These bits may be used by other modules (see the device-specific data sheet). |
USCI_A1/B1 Interrupt Enable Register
UC1IE is shown in Figure 17-29 and described in Table 17-15.
Return to Table 17-2.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Unused | UCB1TXIE | UCB1RXIE | |||||
rw-0 | rw-0 | rw-0 | rw-0 | rw-0 | rw-0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-4 | Unused | R/W | 0h | Unused |
3 | UCB1TXIE | R/W | 0h | USCI_B1 transmit interrupt enable 0b = Interrupt disabled 1b = Interrupt enabled |
2 | UCB1RXIE | R/W | 0h | USCI_B1 receive interrupt enable 0b = Interrupt disabled 1b = Interrupt enabled |
1-0 | These bits may be used by other USCI modules (see the device-specific data sheet). |
USCI_A1/B1 Interrupt Flag Register
UC1IFG is shown in Figure 17-30 and described in Table 17-16.
Return to Table 17-2.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Unused | UCB1TXIFG | UCB1RXIFG | |||||
rw-0 | rw-0 | rw-0 | rw-0 | rw-1 | rw-0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-4 | Unused | R/W | 0h | Unused |
3 | UCB1TXIFG | R/W | 0h | USCI_B1 transmit interrupt flag. UCB1TXIFG is set when UCB1TXBUF is empty. 0b = No interrupt pending 1b = Interrupt pending |
2 | UCB1RXIFG | R/W | 0h | USCI_B1 receive interrupt flag. UCB1RXIFG is set when UCB1RXBUF has received a complete character. 0b = No interrupt pending 1b = Interrupt pending |
1-0 | These bits may be used by other USCI modules (see the device-specific data sheet). |