SLLA602 Application note

SLLA602 March 2024 LM5110 , LM5111 , TPS2811 , TPS2811-Q1 , TPS2812 , TPS2813 , TPS2814 , TPS2815 , UCC27323 , UCC27324 , UCC27324-Q1 , UCC27325 , UCC27423 , UCC27423-EP , UCC27423-Q1 , UCC27424 , UCC27424-EP , UCC27424-Q1 , UCC27425 , UCC27425-Q1 , UCC27444 , UCC27444-Q1 , UCC27523 , UCC27524 , UCC27524A , UCC27524A-Q1 , UCC27524A1-Q1 , UCC27525 , UCC27526 , UCC27527 , UCC27528 , UCC27528-Q1 , UCC27624 , UCC27624-Q1 , UCC37323 , UCC37324 , UCC37325 , UCD7201

4.4 Power Loss Calculations

The equations for power losses in gate driver data sheets are in terms of capacitive loads. In the case of a pulse transformer circuit, the load is inductive and these equations do not apply.

Equation 12.

P = V_{D D} \times Q_{g} \times F_{s w}

The usual power loss equation for capacitive loads takes the charge added and removed from the gate in a switching cycle (Q_g), and multiplies by the switching frequency (F_sw). This multiplication gives the average current from the charging and discharging of the gate. By multiplying the average current by the VDD, the power loss due to switching is given. This equation is per FET, so the number is doubled in a dual channel driver or half-bridge driver.

Even with the transformer coupling, this charge-based method still works to estimate power dissipation. Assuming a lossless transformer, we can divide our initial equation by a factor of two to remove the pull-down (as that is dissipated by the local PNP pull-down). Additionally, we can add the DC leakage of the PNP during the off time. To demonstrate the PNP DC current, here is the same circuit as Figure 2-4 with a 100Ω base resistor.

Figure 4-2 Oscilloscope Capture of Gate Drive Transformer Waveforms With 100Ω R_B

With this R_B change, the leakage current becomes more noticeable than in Figure 2-4. Notice how I_prime does not return to 0A, but stays closer to 100mA. The current in the primary loop is offset by a DC current caused by the PNP. The offset current can be calculated as following:

Equation 13.

I_{B} = \frac{V_{D D} - V_{B E}}{R_{B}}

DC current sourced by the driver during a high output state is the worst-case for this driver due to the hybrid pullup structure. This is because the higher resistance PMOS must source this current. By adding the PNP base current, and RMS magnetizing current into our power dissipation equation, we get the following equation:

Equation 14.

P t o t a l = P_{S W} + P_{D C} + P_{M A G}

Equation 15.

P_{S W} = \frac{V_{D D} \times Q_{g} \times F_{s w} \times 2}{2}

Equation 16.

P_{D C} = {I_{B}}^{2} \times R_{d r i v e r}

Equation 17.

P t o t a l = V_{D D} \times Q_{g} \times F_{s w} + (R o h + R o l) \times [{(\frac{V_{D D} - V_{B E}}{R_{B}})}^{2} + {(\frac{V_{D D} \times t_{o n}}{L_{m a g} \times 2 \times \sqrt{3}})}^{2}]

The numbers can be multiplied to account for transformers with different turns ratios. This equation also demonstrates an important factor in the selection of the PNP. PNPs with high gains are preferable because high gain allows a stronger pull-down (fewer switching losses) with a larger R_B. With R_B values greater than 1kΩ, the leakage can be negligible.