The leveling processes in the DDR3 interface impose an upper limit on the maximum round-trip delay. If this limit is exceeded, the DDR3 interface may fail the leveling process and data corruption may occur. This limit is sufficiently large that well-controlled topologies will not likely exceed the limit.

The round-trip delay for a given SDRAM is defined as the sum of two delays. The first is the longest delay for the clock, command, control, and address groups to that SDRAM. The second is the delay for the data group to that same SDRAM. This round-trip delay must be calculated for each byte-lane to each SDRAM device implemented in the DDR3 memory topology, including SDRAM devices on DIMM. All of these individual sums must be below the limit to help ensure robust operation.

Internally, the DDR3 controller logic has a theoretical upper limit of four clock cycles. There are multiple processes that have variation terms that reduce this time window, as listed below:

• ddrclkout_period – period of reference clock the DSP is providing to SDRAM
• tDQSCK - DQS to CK skew limit from SDRAM data sheet – this is stated for each standard speed grade in the JEDEC DDR3 SDRAM standard
• Invert clock out – delay of half a clock cycle if enabled – option normally used only in very small memory topologies
• adjustment_sum – sum that accounts for all of the leveling errors, buffer delays, and jitter terms associated with the circuitry, and the leveling adjustment – upper limit is defined to be half a clock period plus 225 ps.

The following equation provides an approximation of the maximum round trip delay:

• Case 1: Invert clock out disabled
  • round_trip_delay < (4 * ddrclkout_period) - tDQSCK - adjustment_sum
  • round_trip_delay < (4 * ddrclkout_period) - tDQSCK - 0.5 * ddrclkout_period - 225 ps
  • round_trip_delay < (3.5 * ddrclkout_period) - tDQSCK - 225 ps
• Case 2: Invert clock out enabled (adds an additional half-clock period of delay to the command delay term)
  • round_trip_delay < (4 * ddrclkout_period) - tDQSCK - 0.5 * ddrclkout_period - adjustment_sum
  • round_trip_delay < (4 * ddrclkout_period) - tDQSCK - 0.5 * ddrclkout_period - 0.5 * drclkoutperiod - 225 ps
  • round_trip_delay < (3 * ddrclkout_period) - tDQSCK - 225 ps

Based on the previous equations, the following calculations and summary table show the write leveling skew limitations for both invert clock out enabled and disabled, given the DDR3-1333 and DDR3-1600 JEDEC SDRAM specification. The first column for each speed-grade category lists the maximum write leveling skew in picoseconds. The second column for each lists the maximum write leveling skew in inches assuming a signal propagation rate of 180 ps/in.

For DDR3-1333:

• ddrclkout_period = 1500 ps
• tDQSCK = ±255 ps
• margin = 100 ps
• Case 1: Invert clock out disabled:
  • round_trip_delay < (3.5 * ddrclkout_period) - tDQSCK - 225 ps
  • round_trip_delay < (3.5 * 1500 ps) - 255 ps - 225 ps
  • round_trip_delay < 4770 ps
• Case 2: Invert clock out enabled (adds an additional half-clock period of delay to the command delay term):
  • round_trip_delay < (3 * ddrclkout_period) - tDQSCK - 225 ps
  • round_trip_delay < (3 * 1500 ps) - 255 ps - 225 ps
  • round_trip_delay < 4020 ps

For DDR3-1600:

• ddrclkout_period = 1250 ps
• tDQSCK = ±225 ps
• margin = 100 ps
• Case 1: Invert clock out disabled
  • round_trip_delay < (3.5 * ddrclkout_period) - tDQSCK - 225 ps
  • round_trip_delay < (3.5 * 1250 ps) - 225 ps - 225 ps
  • round_trip_delay < 3925 ps
• Case 2: Invert clock out enabled (adds an additional half-clock period of delay to the command delay term)
  • round_trip_delay < (3 * ddrclkout_period) - tDQSCK - 225 ps
  • round_trip_delay < (3 * 1250 ps) - 225 ps - 225 ps
  • round_trip_delay < 3300 ps

Table 6-9 shows the round trip delay limitations for both invert clock out enabled and disabled. The first column for each lists the maximum round-trip delay in picoseconds. The second column for each lists the maximum routing length in inches assuming a signal propagation rate of 180 ps/in.

Because this is preliminary guidance and some small margin should be subtracted from these delays to account for additional terms such as multi-rank delay skew, TI recommends that the maximum routing lengths be reduced by 10%.