SPRACN9E september   2022  – may 2023 AM67 , AM67A , AM68 , AM68A , AM69 , AM69A , DRA829J , DRA829J-Q1 , DRA829V , DRA829V-Q1 , TDA4AEN-Q1 , TDA4VEN-Q1 , TDA4VM , TDA4VM-Q1

 

  1.   1
  2.   Jacinto 7 LPDDR4 Board Design and Layout Guidelines
  3.   Trademarks
  4. 1Overview
    1. 1.1 Board Designs Supported
    2. 1.2 General Board Layout Guidelines
    3. 1.3 PCB Stack-Up
    4. 1.4 Bypass Capacitors
      1. 1.4.1 Bulk Bypass Capacitors
      2. 1.4.2 High-Speed Bypass Capacitors
    5. 1.5 Velocity Compensation
  5. 2LPDDR4 Board Design and Layout Guidance
    1. 2.1  LPDDR4 Introduction
    2. 2.2  LPDDR4 Device Implementations Supported
    3. 2.3  LPDDR4 Interface Schematics
    4. 2.4  Compatible JEDEC LPDDR4 Devices
    5. 2.5  Placement
    6. 2.6  LPDDR4 Keepout Region
    7. 2.7  Net Classes
    8. 2.8  LPDDR4 Signal Termination
    9. 2.9  LPDDR4 VREF Routing
    10. 2.10 LPDDR4 VTT
    11. 2.11 CK and ADDR_CTRL Topologies
    12. 2.12 Data Group Topologies
    13. 2.13 CK and ADDR_CTRL Routing Specification
    14. 2.14 Data Group Routing Specification
    15. 2.15 Channel, Byte, and Bit Swapping
  6. 3LPDDR4 Board Design Simulations
    1. 3.1 Board Model Extraction
    2. 3.2 Board-Model Validation
    3. 3.3 S-Parameter Inspection
    4. 3.4 Time Domain Reflectometry (TDR) Analysis
    5. 3.5 Simulation Integrity Analysis
      1. 3.5.1 Simulation Setup
      2. 3.5.2 Simulation Parameters
      3. 3.5.3 Simulation Targets
        1. 3.5.3.1 Waveform Quality
        2. 3.5.3.2 Eye Quality
        3. 3.5.3.3 Delay Report
        4. 3.5.3.4 Mask Report
    6. 3.6 Design Example
      1. 3.6.1 Stack-Up
      2. 3.6.2 Routing
      3. 3.6.3 Model Verification
      4. 3.6.4 Simulation Results
  7. 4Revision History

2.13 CK and ADDR_CTRL Routing Specification

Skew within the CK and ADDR_CTRL net classes directly reduces setup and hold margin for the ADDR_CTRL nets. Thus, this skew must be controlled. The routed PCB track has a delay proportional to its length. Thus, the delay skew must be managed through matching the lengths of the routed tracks within a defined group of signals. The only way to practically match skew on a PCB is to lengthen the shorter traces up to the length of the longest net in the net class and its associated clock.

Table 2-6 lists the limits for the individual segments that comprise the routing from the processor to the SDRAM. These segment lengths coincide with the CK and ADDR_CTRL topology diagram shown previously in Table 2-6, Figure 2-7, and Figure 2-8. By controlling the routed lengths for the same segments of all signals in a routing group, the signal delay skews are controlled. Most PCB layout tools can be configured to generate reports to assist with this validation. If this cannot be generated automatically, this must be generated and verified manually.

These parameters are recommendations only, intended to get the design close to success prior to simulation. To ensure the PCB design meets all requirements, it is required the design be simulated and those results compared with the simulation results defined in Section 3.

Table 2-6 CK and ADDR_CTRL Routing Specifications
Number Parameter MIN TYP MAX UNIT
LP4_ACRS1 Propagation delay of net class CK
RSAC1 + RSAC2		 250 (1) ps
LP4_ACRS2 Propagation delay of net class ADDR_CTRL
RSAC3 + RSAC4, RSAC5		 250 (1) ps
LP4_ACRS3 Skew within net class CK (CK+ to CK- Skew)
(RSAC1 + RSAC2) Skew		 0.25 (2) ps
LP4_ACRS4 Skew across net class ADDR_CTRL
RSAC3 + RSAC4 Skew		 3 ps
LP4_ACRS5 Skew between each T-branch signal pair
RSAC2 or RSAC4 Skew (7)		 0.1 ps
LP4_ACRS6 Skew across ADDR_CTRL and associated CK clock net class
RSAC1+ RSAC2, RSAC3 + RSAC4, RSAC5 (9)		 3 ps
LP4_ACRS7 Vias per trace 4 vias
LP4_ACRS8 Via Stub Length (8) 20 Mils
LP4_ACRS8 Via count difference 0 (3) vias
LP4_ACRS10 Center-to-center CK to other LPDDR4 trace spacing (4) 4w
LP4_ACRS11 Center-to-center ADDR_CTRL to other LPDDR4 trace spacing (4) 3w
LP4_ACRS12 Center-to-center ADDR_CTRL to other ADDR_CTRL trace spacing (4) 3w
LP4_ACRS13 CK center-to-center spacing (5), (6)
LP4_ACRS14 CK spacing to other net (4) 4w
(1) Max value is based upon conservative signal integrity approach. This value could be extended only if detailed signal integrity analysis of rise time and fall time confirms desired operation.
(2) To be verified by design/simulation only. Not expected to be validated on design.
(3) Via count difference may increase by 1 only if accurate 3-D modeling of the signal flight times – including accurately modeled signal propagation through vias – has been applied to ensure all segment skew maximums are not exceeded.
(4) Center-to-center spacing is allowed to fall to minimum 2w for up to 500 mils of routed length (only near endpoints).
(5) CK spacing set to ensure proper differential impedance.
(6) The user must control the impedance so that inadvertent impedance mismatches are not created. Generally speaking, center-to center spacing should be either 2w or slightly larger than 2w to achieve a differential impedance equal to twice the single-ended impedance, Zo, on that layer.
(7) Skew control on branch trace segments (Balance T) is intended to optimize signal integrity (waveform reflections). It is not required nor recommended to match skew across all branch trace segments, just for each branch of a specific signal.
(8) Via stub control is required if operating LPDDR4 above 3200 Mbps.
(9) Recommend routing net classes CK and ADDR_CTRL on same signal layer for better skew control.