SPRACN9E september   2022  – may 2023 AM67 , AM67A , AM68 , AM68A , AM69 , AM69A , DRA829J , DRA829J-Q1 , DRA829V , DRA829V-Q1 , TDA4AEN-Q1 , TDA4VEN-Q1 , TDA4VM , TDA4VM-Q1

 

  1.   1
  2.   Jacinto 7 LPDDR4 Board Design and Layout Guidelines
  3.   Trademarks
  4. 1Overview
    1. 1.1 Board Designs Supported
    2. 1.2 General Board Layout Guidelines
    3. 1.3 PCB Stack-Up
    4. 1.4 Bypass Capacitors
      1. 1.4.1 Bulk Bypass Capacitors
      2. 1.4.2 High-Speed Bypass Capacitors
    5. 1.5 Velocity Compensation
  5. 2LPDDR4 Board Design and Layout Guidance
    1. 2.1  LPDDR4 Introduction
    2. 2.2  LPDDR4 Device Implementations Supported
    3. 2.3  LPDDR4 Interface Schematics
    4. 2.4  Compatible JEDEC LPDDR4 Devices
    5. 2.5  Placement
    6. 2.6  LPDDR4 Keepout Region
    7. 2.7  Net Classes
    8. 2.8  LPDDR4 Signal Termination
    9. 2.9  LPDDR4 VREF Routing
    10. 2.10 LPDDR4 VTT
    11. 2.11 CK and ADDR_CTRL Topologies
    12. 2.12 Data Group Topologies
    13. 2.13 CK and ADDR_CTRL Routing Specification
    14. 2.14 Data Group Routing Specification
    15. 2.15 Channel, Byte, and Bit Swapping
  6. 3LPDDR4 Board Design Simulations
    1. 3.1 Board Model Extraction
    2. 3.2 Board-Model Validation
    3. 3.3 S-Parameter Inspection
    4. 3.4 Time Domain Reflectometry (TDR) Analysis
    5. 3.5 Simulation Integrity Analysis
      1. 3.5.1 Simulation Setup
      2. 3.5.2 Simulation Parameters
      3. 3.5.3 Simulation Targets
        1. 3.5.3.1 Waveform Quality
        2. 3.5.3.2 Eye Quality
        3. 3.5.3.3 Delay Report
        4. 3.5.3.4 Mask Report
    6. 3.6 Design Example
      1. 3.6.1 Stack-Up
      2. 3.6.2 Routing
      3. 3.6.3 Model Verification
      4. 3.6.4 Simulation Results
  7. 4Revision History

3.5.2 Simulation Parameters

It is important to configure the simulation to exercise the system to real, but worst case parameters.

  • Use the worst-case bit pattern to excite the system. The simulator should be able to generate the worst-case bit pattern based on channel characterization.
  • Select the controller and DRAM models (sets the drive strength, ODT, VOH levels, and so forth) from the IBIS files which work best for the system.
    • This is typically an iterative process.
    • Every system is unique and the optimal settings for these parameters can vary from system to system.
      Table 3-1 Example Data Write ODI/ODT Optimization
      Pkg Byte Board ODI Ω ODT Ω Total EW Margin (ps) Total EH Margin (mV)B
      B3 J7 370HR 10L Ref B3, No BD 40 40 50.28 15.66
      B3 J7 370HR 10L Ref B3, No BD 40 48 27.62 11.76
      B3 J7 370HR 10L Ref B3, No BD 40 40 33.52 2.92
      B3 J7 370HR 10L Ref B3, No BD 48 48 1.54 0.86
  • Data bus and address bus ODT and drive strength values can be set independently. As an example, the J721E EVM used 40-Ω ODT for data read/writes and 80-Ω for CA bus. Drive strength of 40-ohms for data read/write and CA.
    • Data READ Controller model - lpddr4_odt_40, lpddr4_odt_40_diff
    • Data WRITE Controller model - lpddr4_ocd_40p_40n, lpddr4_ocd_40p_40n_diff
    • CA/CLK Controller model - lpddr4_ocd_40p_40n, lpddr4_ocd_40p_40n_diff
  • Set up the channel simulation parameters. These typically consists of the data rate, ignore time/bits, minimum number of bits, bit sampling rate, BER floor, number of bits for display, types of BER eyes (voltage and/or timing), and target BER.
    • To determine the minimum number of bits one can run a series of channel simulations with different number of bits. The BER signal eye (and margins) tend to converge after a certain minimum number of bits. This should help determining the minimum number of bits to be used for the system.
    • Run channel simulations to generate the eye diagrams at LBER of -16.
  • Run channel simulations with non-ideal power settings at different PVT corners. It is recommended to run the simulations at least at the SSHT and FFLT corners.