SPRACN9E september 2022 – may 2023 AM67 , AM67A , AM68 , AM68A , AM69 , AM69A , DRA829J , DRA829J-Q1 , DRA829V , DRA829V-Q1 , TDA4AEN-Q1 , TDA4VEN-Q1 , TDA4VM , TDA4VM-Q1
The LPDDR4 interface schematics vary, depending upon the number of ranks implemented. General connectivity is straightforward and consistent between the implementations. Figure 2-1 illustrates a 32-bit, single-rank LPDDR4 implementation. If dual rank is required, the additional chip select is included. Figure 2-2 illustrates a 32-bit, dual-rank LPDDR4 implementation. On select devices, 16-bit single-rank LPDDR4 implementation are support, see Figure 2-3.