SPRAD12A July   2022  – February 2023 TMS320F280021 , TMS320F280021-Q1 , TMS320F280023 , TMS320F280023-Q1 , TMS320F280023C , TMS320F280025 , TMS320F280025-Q1 , TMS320F280025C , TMS320F280025C-Q1 , TMS320F280033 , TMS320F280034 , TMS320F280034-Q1 , TMS320F280036-Q1 , TMS320F280036C-Q1 , TMS320F280037 , TMS320F280037-Q1 , TMS320F280037C , TMS320F280037C-Q1 , TMS320F280038-Q1 , TMS320F280038C-Q1 , TMS320F280039 , TMS320F280039-Q1 , TMS320F280039C , TMS320F280039C-Q1 , TMS320F280040-Q1 , TMS320F280040C-Q1 , TMS320F280041 , TMS320F280041-Q1 , TMS320F280041C , TMS320F280041C-Q1 , TMS320F280045 , TMS320F280048-Q1 , TMS320F280048C-Q1 , TMS320F280049 , TMS320F280049-Q1 , TMS320F280049C , TMS320F280049C-Q1 , TMS320F28075 , TMS320F28075-Q1 , TMS320F28076 , TMS320F28374D , TMS320F28374S , TMS320F28375D , TMS320F28375S , TMS320F28375S-Q1 , TMS320F28376D , TMS320F28376S , TMS320F28377D , TMS320F28377D-EP , TMS320F28377D-Q1 , TMS320F28377S , TMS320F28377S-Q1 , TMS320F28378D , TMS320F28378S , TMS320F28379D , TMS320F28379D-Q1 , TMS320F28379S , TMS320F28384D , TMS320F28384D-Q1 , TMS320F28384S , TMS320F28384S-Q1 , TMS320F28386D , TMS320F28386D-Q1 , TMS320F28386S , TMS320F28386S-Q1 , TMS320F28388D , TMS320F28388S , TMS320F28P550SJ , TMS320F28P559SJ-Q1 , TMS320F28P650DH , TMS320F28P650DK , TMS320F28P650SH , TMS320F28P650SK , TMS320F28P659DK-Q1

 

  1.   Abstract
  2.   Trademarks
  3. 1 Introduction
  4. 2 SysConfig
  5. 3 Time-Base (TB) Submodule
    1. 3.1 Setting the Frequency
    2. 3.2 Applying a Phase Shift
    3. 3.3 Setting up the Synchronization (Sync) Scheme
  6. 4 Counter-Compare (CC) and Action-Qualifier (AQ) Submodules
    1. 4.1 Calculating the Duty Cycle
  7. 5 Deadband (DB) Submodule
    1. 5.1 Setting up Signal Pairs
  8. 6 Verifying the Output
    1. 6.1 Checking the Duty Cycle and Dead-Time Insertion
    2. 6.2 Checking the Phase Shift Applied
  9. 7 Trip-Zone (TZ) and Digital Compare (DC) Submodules
    1. 7.1 Drive Outputs Low for an ePWM Cycle Upon Trip Condition Set Through CMPSS
    2. 7.2 Drive Outputs Low Until Cleared Through Software Upon Trip Condition set Through GPIO
  10. 8 Event-Trigger (ET) Submodule
    1. 8.1 Setting Up Time-Base Interrupts
  11. 9 Global Load
    1. 9.1 Applying Global Loading and One-Shot Load Feature
    2. 9.2 Linking the ePWM Modules
    3. 9.3 Updating Action Qualifier Settings and Counter Compare Values Through Global Loading
  12. 10Summary
  13. 11References
  14. 12Revision History

3.3 Setting up the Synchronization (Sync) Scheme

#GUID-68570934-B904-4F88-8D7F-B81C32A3FFAC shows how to set the phase shift value within SysConfig.

Now that the required time-base phase shift values are known, you can set up the synchronization scheme between the three ePWM modules. The ePWM type-4 module has two different sync schemes. Focus on the latest sync scheme for the type-4 module. For this sync scheme, each ePWM module has a synchronization input (SYNCIN), a synchronization output (SYNCO), and a peripheral synchronization output (SYNCPER).

GUID-C6F94125-A1AD-4AFE-8977-9EB8F824A712-low.gifFigure 3-2 Synchronization Scheme

Since EPWM1 is the sync source, all that needs to be set up is the SYNCO, which is what drives the sync chain. There are many options to choose as the SYNCO of EPWM1, such as when the time-base counter is equal to zero or period. In this use-case, you can generate the SYNCO when the time-base counter of EPWM1 is equal to zero.

Figure 3-3 EPWM Time Base: Configuration for EPWM1 as the Sync Source

The following code is generated from SysConfig for EPWM1:

EPWM_enableSyncOutPulseSource(myEPWM1_BASE, EPWM_SYNC_OUT_PULSE_ON_CNTR_ZERO);

For EPWM2 and EPWM3, the SYNCIN comes from EPWM1’s SYNCO. The SYNCO occurs whenever the time-base counter is equal to zero. This way, both EPWM2 and EPWM3 receive the SYNCO signal from EPWM1.

For sync receivers such as EPWM2 and EPWM3, it is important to enable the phase shift and provide a phase shift value. An example of this configuration is shown in #FIG_C1F_3BV_4TB.

Figure 3-4 ePWM Time Base: Configuration for EPWM2 Sync Receiver Setup

The following code is generated from SysConfig for EPWM2 and EPWM3:

// EPWM 2
EPWM_enablePhaseShiftLoad(myEPWM2_BASE); 
EPWM_setPhaseShift(myEPWM2_BASE, 42); 
EPWM_setSyncInPulseSource(myEPWM2_BASE, EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM1); 
EPWM_enableSyncOutPulseSource(myEPWM2_BASE, EPWM_SYNC_OUT_PULSE_ON_CNTR_ZERO);
// EPWM 3
EPWM_enablePhaseShiftLoad(myEPWM3_BASE);  
EPWM_setPhaseShift(myEPWM3_BASE, 83);  
EPWM_setSyncInPulseSource(myEPWM3_BASE, EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM1);  
EPWM_enableSyncOutPulseSource(myEPWM3_BASE, EPWM_SYNC_OUT_PULSE_ON_CNTR_ZERO);