AM263x is a system on chip (SoC) with Arm® Cortex®-R5F clusters and a dedicated accelerator for real time control. The clusters can be configured as either dual core mode or lockstep mode. And, the accelerator is named as control subsystem and includes interface modules like ADC, DAC, and PWM. This work takes core 0-0 as an example and demonstrates features of one R5F core and a group of interface modules for one traction inverter. This section gives a brief introduction on the R5F cluster and the control sub-system. More details on the SoC can be found in the AM263x Sitara™ Microcontrollers Data Sheet and the AM263x Sitara Processors Technical Reference Manual. Details on inverter hardware can be found in the ASIL D Safety Concept-Assessed High-Speed Traction, Bi-directional DC/DC Conversion Reference Design.
The Arm® Cortex®-R5F cluster includes two R5F cores accompanying memories like L1 cache and tightly-coupled memories (TCM), standard Arm CoreSight™ debug and trace architecture, integrated vectored interrupt manager (VIM), ECC aggregators, and various other modules for protocol conversion and address translation for easy integration into the SoC. More detailed block diagram can be found in AM263x technical reference manual. The key to solve real time control problem is to understand the impacts from cache and TCM. Instructions and data can be allocated to either On-Chip RAM or TCM by link command file when program is built. During execution, frequently used instructions and data in On-Chip RAM will be taken into cache automatically. As a result, execution time is significantly improved. But, the data in On-Chip RAM is not updated until it is written back from cache. When data is in cache, the only way to access is via instructions running in the core and memory view from integrated development environment (IDE) like Code Composer Studio™ (CCS) is not able to read cache. However, there is a way to read cache with CCS via a section of program operating universal asynchronous receiver/transmitter (UART) inside the core. Details on the UART method will be introduced in a following section. On the other hand, instructions and data allocated to TCM are kept at the address and available to memory view all the time. Generally, execution time of program in cache and TCM is very close but that of program in On-Chip RAM is much slower. And, the operation transferring program from On-Chip RAM to cache takes some time and introduces some non-predictive latency. If the latency is significant to the requirement from application, it is highly encouraged to store the application program in TCM. Details on TCM address can be found in AM263x technical reference manual. In this work, the interrupt program for field oriented control and software resolver to digital converter are located in TCM. The link command file is available as an example in CCS project folder.
The accelerator for real time control inherits Texas Instrument’s classic C2000 control modules widely used around the world. It includes Analog-to-Digital Converter (ADC), Analog Comparator, Buffered Digital-to-Analog Converter, Enhanced Pulse Width Modulator (EPWM), Enhanced Capture, Enhanced Quadrature Encoder Pulse, Fast Serial Interface, Sigma Delta Filter Module, and Crossbar. Details on the modules are available in AM263x technical reference manual. With the help of an intuitive system configuration tool, SYSCONFIG, it is also possible to configure those modules with reduced exposure to implementation details. Details on SYSCONFIG can be found in AM263x Software Development Kit (SDK). The key for module synchronization is to configure PWM synchronization input/output in EPWM Time Base section and ADC Start-of-Conversion (SOC) trigger in EPWM Event-Trigger section. Time Base is to align multiple PWM channels while Event-Trigger is to synchronize features like ADC, DMA and Interrupt. One example for traction inverter is located in CCS project folder of traction inverter demo. In the example, one PWM channel is set to trigger updates for resolver excitation signal via DMA and DAC at higher frequency, and three PWM channels are used to create inverter signal and generate ADC SOC. In this way, resolver excitation signal from DAC is aligned to the desired phase for ADC samples. Multiple ADC units can share the same SOC. In other words, multiple samples can be taken simultaneously across multiple ADC units. Within one ADC unit, the sequence of samples can be configured in SOC Configuration section. And, ADC interrupt can be set in INT Configuration. The interrupt can be triggered at either the start of one ADC conversion or the end of one ADC conversion. Some simple examples on PWM and ADC are available in AM263x SDK under "\examples\drivers\epwm" and "\examples\drivers\adc". More details on the APIs can be found in AM263x SDK under "\source\drivers". The header files have great details in comments.
As we mentioned, there are some topics to be considered in development, like SoC architecture and SDK APIs. More details on those can be found in AM263x technical reference manual and SDK package. In the following sections, this work is going to focus on how to use the example project as a framework to accelerate development of traction inverter, and how to migrate existing project code to AM263x.
The framework includes the resources highlighted in Figure 1-1 and is built into the traction system in Figure 1-2. TIDM-02009 is the traction inverter reference design hardware. It includes a power model, gate drivers, current and voltage samples, resolver analog front end, and some connection interfaces. The motor includes a resolver taking sine wave excitation and sending modulated feedbacks for position sensing. Field Oriented Control is implemented with Cluster-0 Core-0. The real-time control section in ADC INT1 is allocated to TCM for the most deterministic execution time.