SPRUIM2H May 2020 – October 2023 AM2431 , AM2432 , AM2434 , AM6411 , AM6412 , AM6421 , AM6422 , AM6441 , AM6442
For the outgoing data, the MII_G_RT calculates the CRC32 value and inserts it into outgoing packets. The CRC value computed on each MII transmit path is also available in memory map registers that can be read by the PRU and used primarily for debug and diagnostic purposes. The CRC is inserted into the outgoing packet based on the commands received through the R31 register of the PRU. The CRC will be inserted into the TX L1 FIFO, and there must be enough room to store the CRC value in the FIFO or else the FIFO will overflow. As Table 6-470 shows, the CRC programming model supports three sequences that provide more flexibility. Note: “cmdR31” indicates write to the mentioned bits of the R31 command interface.
Option 1 | Step 1: cmdR31 [TX_CRC_HIGH + TX_CRC_LOW + TX_EOF] |
Option 2 | Note: Only valid when TX L2 is disabled. Step 1: cmdR31 [TX_CRC_HIGH] |
Step 2: wait > 6 clocks (PRU cycles) | |
Step 3: cmdR31 [TX_CRC_LOW + TX_EOF] | |
Option 3 | Note: Only valid when TX L2 is disabled. Step 1: cmdR31 [TX_CRC_HIGH] |
Step 2: wait > 6 clocks (PRU cycles) | |
Step 3: read TX_CRC0[31-0] TX_CRC0 and TX_CRC1[31-0] TX_CRC1 | |
Step 4: modify CRC[15-0] | |
Step 5: cmdR31 [TX_PUSH16 + TX_EOF + TX_ERROR_NIBBLE] |