SPRUIM2H May 2020 – October 2023 AM2431 , AM2432 , AM2434 , AM6411 , AM6412 , AM6421 , AM6422 , AM6441 , AM6442
The PRU_ICSSG implements an enhanced General Purpose Input/Output (GPIO) module that supports two general-purpose output modes: direct output and shift out.
Table 6-414 describes these modes in detail.
Each PRU core can only be configured for one GPO mode at a time. Each mode uses the same R30 signals and internal register bits for different purposes. A summary is found in Table 6-414.
The ICSSG_GPCFG0_REG register, bitfield [29-26] PR1_PRU0_GP_MUX_SEL (PRU0 or PRU1) in the PRU_ICSSG CFG register space needs to be set to 0h for GP mode. For a given PRU core, the following IO modes are mutually exclusive: GP mode, Sigma Delta mode, and 3 channel Peripheral I/F mode.
Mode | Function | Configuration |
---|---|---|
Direct output | pru<n>_r30[19:0] feeds directly to GPO[19:0] | Default state |
Shift out |
| Enabled by ICSSG_GPCFG0_REG register (PRU0 or PRU1) Free Running Clock or Fixed Clock Count Mode selected by ICSSG_GPECFG0_REG register. |
Pad Names at Device Level (1) | GPO Modes | |
---|---|---|
Direct output | Shift out | |
PRG<k>_PRU<n>_GPO0 | GPO0 | DATAOUT |
PRG<k>_PRU<n>_GPO1 | GPO1 | CLOCKOUT |
PRG<k>_PRU<n>_GPO2 | GPO2 | |
PRG<k>_PRU<n>_GPO3 | GPO3 | |
PRG<k>_PRU<n>_GPO4 | GPO4 | |
PRG<k>_PRU<n>_GPO5 | GPO5 | |
PRG<k>_PRU<n>_GPO6 | GPO6 | |
PRG<k>_PRU<n>_GPO7 | GPO7 | |
PRG<k>_PRU<n>_GPO8 | GPO8 | |
PRG<k>_PRU<n>_GPO9 | GPO9 | |
PRG<k>_PRU<n>_GPO10 | GPO10 | |
PRG<k>_PRU<n>_GPO11 | GPO11 | |
PRG<k>_PRU<n>_GPO12 | GPO12 | |
PRG<k>_PRU<n>_GPO13 | GPO13 | |
PRG<k>_PRU<n>_GPO14 | GPO14 | |
PRG<k>_PRU<n>_GPO15 | GPO15 | |
PRG<k>_PRU<n>_GPO16 | GPO16 | |
PRG<k>_PRU<n>_GPO17 | GPO17 | |
PRG<k>_PRU<n>_GPO18 | GPO18 | |
PRG<k>_PRU<n>_GPO19 | GPO19 |