SPRUIM2H May 2020 – October 2023 AM2431 , AM2432 , AM2434 , AM6411 , AM6412 , AM6421 , AM6422 , AM6441 , AM6442
This section describes the MCU_M4FSS integration in the device, including information about clocks, resets, and hardware requests.
Figure 6-153 shows the MCU_M4FSS0 integration.
Module Instance | Attributes | ||||
Power Sleep Controller | Power Domain | Module Domain | Interconnect | ||
MCU_M4FSS0 | MCU_M4FSS0_CLUSTER | MCU_PSC0 | PD0 | LPSC0 | MCU_CBASS0 |
MCU_M4FSS0_CORE0 | MCU_PSC0 | PD1 | LPSC7 | MCU_CBASS0 |
Clocks | |||||
Module Instance | Module Clock Input | Source Clock Signal | Source | Description | |
MCU_M4FSS0 | MCU_M4FSS0_VBUS_CLK | MCU_SYSCLK0 or MCU_SYSCLK0/2(1) | MCU_PLLCTRL0 | Main module clock that drive drives majority of blocks including M4F in functional mode. | |
MCU_M4FSS0_DAP_CLK | MCU_SYSCLK0/2 | MCU_PLLCTRL0 | Module DAP clock. | ||
Resets | |||||
Module Instance | Module Reset Input | Source Reset Signal | Source | Description | |
MCU_M4FSS0 | MCU_M4FSS0_POR_RST | MOD_POR_RST | LPSC0 | Module POR reset | |
MCU_M4FSS0_GLOBAL_RST | MOD_G_RST | LPSC0 | Module global (main) reset | ||
MCU_M4FSS0_LOCAL_RST | MOD_L_RST | LPSC7 | Module local reset (for M4F core) |
Interrupt Requests | |||||
Module Instance | Module Interrupt Signal | Destination Interrupt Input | Destination | Description | Type |
MCU_M4FSS0 | MCU_M4FSS0_RAT_0_EXP_INTR_0 | MCU_M4FSS0_CORE0_NVIC_IN_14 | MCU_M4FSS0 | RAT exception error | Level |
MCU_M4FSS0_ECC_AGGR_0_ECC_CORRECTED_ERR_LEVEL_0 | MCU_ESM0_LVL_IN_4 | MCU_ESM0 | ECC correctable error | Level | |
MCU_M4FSS0_ECC_AGGR_0_ECC_UNCORRECTED_ERR_LEVEL_0 | MCU_ESM0_LVL_IN_5 | MCU_ESM0 | ECC uncorrectable error | Level |
MCU_M4FSS interrupts are further described in Section 6.3.3.9, MCU_M4FSS Interrupts.
For more information on the interconnects, see Chapter 3, System Interconnect.
For more information on the power, reset and clock management, see the corresponding sections within Chapter 5, Device Configuration.
For more information on the device interrupt controllers, see Section 9.2, Interrupt Controllers.