SPRUIM2H May 2020 – October 2023 AM2431 , AM2432 , AM2434 , AM6411 , AM6412 , AM6421 , AM6422 , AM6441 , AM6442
Offset | Length | Acronym | Register Name | A53SS0 Physical Address |
---|---|---|---|---|
0h | 32 | A53SS0_rev | Aggregator Revision Register | 0071 7000h |
8h | 32 | A53SS0_vector | ECC Vector Register | 0071 7008h |
Ch | 32 | A53SS0_stat | Misc Status | 0071 700Ch |
10h | 32 | A53SS0_reserved_svbus | Reserved Area for Serial VBUS Registers | 0071 7010h |
3Ch | 32 | A53SS0_sec_eoi_reg | EOI Register | 0071 703Ch |
40h | 32 | A53SS0_sec_status_reg0 | Interrupt Status Register 0 | 0071 7040h |
80h | 32 | A53SS0_sec_enable_set_reg0 | Interrupt Enable Set Register 0 | 0071 7080h |
C0h | 32 | A53SS0_sec_enable_clr_reg0 | Interrupt Enable Clear Register 0 | 0071 70C0h |
13Ch | 32 | A53SS0_ded_eoi_reg | EOI Register | 0071 713Ch |
140h | 32 | A53SS0_ded_status_reg0 | Interrupt Status Register 0 | 0071 7140h |
180h | 32 | A53SS0_ded_enable_set_reg0 | Interrupt Enable Set Register 0 | 0071 7180h |
1C0h | 32 | A53SS0_ded_enable_clr_reg0 | Interrupt Enable Clear Register 0 | 0071 71C0h |
200h | 32 | A53SS0_aggr_enable_set | AGGR interrupt enable set Register | 0071 7200h |
204h | 32 | A53SS0_aggr_enable_clr | AGGR interrupt enable clear Register | 0071 7204h |
208h | 32 | A53SS0_aggr_status_set | AGGR interrupt status set Register | 0071 7208h |
20Ch | 32 | A53SS0_aggr_status_clr | AGGR interrupt status clear Register | 0071 720Ch |
Offset | Length | Acronym | Register Name | A53SS0 Physical Address |
---|---|---|---|---|
0h | 32 | A53SS0_rev | Aggregator Revision Register | 0071 7400h |
8h | 32 | A53SS0_vector | ECC Vector Register | 0071 7408h |
Ch | 32 | A53SS0_stat | Misc Status | 0071 740Ch |
10h | 32 | A53SS0_reserved_svbus | Reserved Area for Serial VBUS Registers | 0071 7410h |
3Ch | 32 | A53SS0_sec_eoi_reg | EOI Register | 0071 743Ch |
40h | 32 | A53SS0_sec_status_reg0 | Interrupt Status Register 0 | 0071 7440h |
80h | 32 | A53SS0_sec_enable_set_reg0 | Interrupt Enable Set Register 0 | 0071 7480h |
C0h | 32 | A53SS0_sec_enable_clr_reg0 | Interrupt Enable Clear Register 0 | 0071 74C0h |
13Ch | 32 | A53SS0_ded_eoi_reg | EOI Register | 0071 753Ch |
140h | 32 | A53SS0_ded_status_reg0 | Interrupt Status Register 0 | 0071 7540h |
180h | 32 | A53SS0_ded_enable_set_reg0 | Interrupt Enable Set Register 0 | 0071 7580h |
1C0h | 32 | A53SS0_ded_enable_clr_reg0 | Interrupt Enable Clear Register 0 | 0071 75C0h |
200h | 32 | A53SS0_aggr_enable_set | AGGR interrupt enable set Register | 0071 7600h |
204h | 32 | A53SS0_aggr_enable_clr | AGGR interrupt enable clear Register | 0071 7604h |
208h | 32 | A53SS0_aggr_status_set | AGGR interrupt status set Register | 0071 7608h |
20Ch | 32 | A53SS0_aggr_status_clr | AGGR interrupt status clear Register | 0071 760Ch |
Offset | Length | Acronym | Register Name | A53SS0 Physical Address |
---|---|---|---|---|
0h | 32 | A53SS0_rev | Aggregator Revision Register | 0071 7800h |
8h | 32 | A53SS0_vector | ECC Vector Register | 0071 7808h |
Ch | 32 | A53SS0_stat | Misc Status | 0071 780Ch |
10h | 32 | A53SS0_reserved_svbus | Reserved Area for Serial VBUS Registers | 0071 7810h |
3Ch | 32 | A53SS0_sec_eoi_reg | EOI Register | 0071 783Ch |
40h | 32 | A53SS0_sec_status_reg0 | Interrupt Status Register 0 | 0071 7840h |
80h | 32 | A53SS0_sec_enable_set_reg0 | Interrupt Enable Set Register 0 | 0071 7880h |
C0h | 32 | A53SS0_sec_enable_clr_reg0 | Interrupt Enable Clear Register 0 | 0071 78C0h |
13Ch | 32 | A53SS0_ded_eoi_reg | EOI Register | 0071 793Ch |
140h | 32 | A53SS0_ded_status_reg0 | Interrupt Status Register 0 | 0071 7940h |
180h | 32 | A53SS0_ded_enable_set_reg0 | Interrupt Enable Set Register 0 | 0071 7980h |
1C0h | 32 | A53SS0_ded_enable_clr_reg0 | Interrupt Enable Clear Register 0 | 0071 79C0h |
200h | 32 | A53SS0_aggr_enable_set | AGGR interrupt enable set Register | 0071 7A00h |
204h | 32 | A53SS0_aggr_enable_clr | AGGR interrupt enable clear Register | 0071 7A04h |
208h | 32 | A53SS0_aggr_status_set | AGGR interrupt status set Register | 0071 7A08h |
20Ch | 32 | A53SS0_aggr_status_clr | AGGR interrupt status clear Register | 0071 7A0Ch |
Short Description: Aggregator Revision Register
Long Description:
Return to Summary Table
Instance Name | Base Address |
---|---|
A53SS0 | 0071 7000h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
SCHEME | BU | MODULE_ID | |||||||||||||
R | R | R | |||||||||||||
1 | 10 | 11010100000 | |||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
REVRTL | REVMAJ | CUSTOM | REVMIN | ||||||||||||
R | R | R | R | ||||||||||||
101 | 10 | 0 | 1 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 - 30 | SCHEME | R | 1h | Scheme |
29 - 28 | BU | R | 2h | bu |
27 - 16 | MODULE_ID | R | 6A0h | Module ID |
15 - 11 | REVRTL | R | 5h | RTL version |
10 - 8 | REVMAJ | R | 2h | Major version |
7 - 6 | CUSTOM | R | 0h | Custom version |
5 - 0 | REVMIN | R | 1h | Minor version |
Short Description: ECC Vector Register
Long Description:
Return to Summary Table
Instance Name | Base Address |
---|---|
A53SS0 | 0071 7008h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | RD_SVBUS_DONE | RD_SVBUS_ADDRESS | |||||||||||||
NONE | R/W1TC | R/W | |||||||||||||
0 | 0 | ||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RD_SVBUS | RESERVED | ECC_VECTOR | |||||||||||||
R/W1TS | NONE | R/W | |||||||||||||
0 | 0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
RESERVED | NONE | Reserved | ||
24 | RD_SVBUS_DONE | R/W1TC | 0h | Status to indicate if read on serial VBUS is complete, write of any value will clear this bit. |
23 - 16 | RD_SVBUS_ADDRESS | R/W | 0h | Read address |
15 | RD_SVBUS | R/W1TS | 0h | Write 1 to trigger a read on the serial VBUS |
RESERVED | NONE | Reserved | ||
10 - 0 | ECC_VECTOR | R/W | 0h | Value written to select the corresponding ECC RAM for control or status |
Short Description: Misc Status
Long Description:
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Instance Name | Base Address |
---|---|
A53SS0 | 0071 700Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
NONE | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | NUM_RAMS | ||||||||||||||
NONE | R | ||||||||||||||
11000 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
RESERVED | NONE | Reserved | ||
10 - 0 | NUM_RAMS | R | 18h | Indicates the number of RAMS serviced by the ECC aggregator |
Short Description: Reserved Area for Serial VBUS Registers
Long Description:
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Instance Name | Base Address |
---|---|
A53SS0 | 0071 7010h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
DATA | |||||||||||||||
R/W | |||||||||||||||
0 | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DATA | |||||||||||||||
R/W | |||||||||||||||
0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 - 0 | DATA | R/W | 0h | Serial VBUS register data |
Short Description: EOI Register
Long Description:
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Instance Name | Base Address |
---|---|
A53SS0 | 0071 703Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
NONE | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | EOI_WR | ||||||||||||||
NONE | R/W1TS | ||||||||||||||
0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
RESERVED | NONE | Reserved | ||
0 | EOI_WR | R/W1TS | 0h | EOI Register |
Short Description: Interrupt Status Register 0
Long Description:
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Instance Name | Base Address |
---|---|
A53SS0 | 0071 7040h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | A53_DUAL_U_L2_DATARAM_SPRAM_7_ECC_SVBUS_PEND | A53_DUAL_U_L2_DATARAM_SPRAM_6_ECC_SVBUS_PEND | A53_DUAL_U_L2_DATARAM_SPRAM_5_ECC_SVBUS_PEND | A53_DUAL_U_L2_DATARAM_SPRAM_4_ECC_SVBUS_PEND | A53_DUAL_U_L2_DATARAM_SPRAM_3_ECC_SVBUS_PEND | A53_DUAL_U_L2_DATARAM_SPRAM_2_ECC_SVBUS_PEND | A53_DUAL_U_L2_DATARAM_SPRAM_1_ECC_SVBUS_PEND | A53_DUAL_U_L2_DATARAM_SPRAM_0_ECC_SVBUS_PEND | |||||||
NONE | R/W1TS | R/W1TS | R/W1TS | R/W1TS | R/W1TS | R/W1TS | R/W1TS | R/W1TS | |||||||
0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | ||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
A53_DUAL_U_L2_TAGRAM_SPRAM_WAY15_ECC_SVBUS_PEND | A53_DUAL_U_L2_TAGRAM_SPRAM_WAY14_ECC_SVBUS_PEND | A53_DUAL_U_L2_TAGRAM_SPRAM_WAY13_ECC_SVBUS_PEND | A53_DUAL_U_L2_TAGRAM_SPRAM_WAY12_ECC_SVBUS_PEND | A53_DUAL_U_L2_TAGRAM_SPRAM_WAY11_ECC_SVBUS_PEND | A53_DUAL_U_L2_TAGRAM_SPRAM_WAY10_ECC_SVBUS_PEND | A53_DUAL_U_L2_TAGRAM_SPRAM_WAY9_ECC_SVBUS_PEND | A53_DUAL_U_L2_TAGRAM_SPRAM_WAY8_ECC_SVBUS_PEND | A53_DUAL_U_L2_TAGRAM_SPRAM_WAY7_ECC_SVBUS_PEND | A53_DUAL_U_L2_TAGRAM_SPRAM_WAY6_ECC_SVBUS_PEND | A53_DUAL_U_L2_TAGRAM_SPRAM_WAY5_ECC_SVBUS_PEND | A53_DUAL_U_L2_TAGRAM_SPRAM_WAY4_ECC_SVBUS_PEND | A53_DUAL_U_L2_TAGRAM_SPRAM_WAY3_ECC_SVBUS_PEND | A53_DUAL_U_L2_TAGRAM_SPRAM_WAY2_ECC_SVBUS_PEND | A53_DUAL_U_L2_TAGRAM_SPRAM_WAY1_ECC_SVBUS_PEND | A53_DUAL_U_L2_TAGRAM_SPRAM_WAY0_ECC_SVBUS_PEND |
R/W1TS | R/W1TS | R/W1TS | R/W1TS | R/W1TS | R/W1TS | R/W1TS | R/W1TS | R/W1TS | R/W1TS | R/W1TS | R/W1TS | R/W1TS | R/W1TS | R/W1TS | R/W1TS |
0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
RESERVED | NONE | Reserved | ||
23 | A53_DUAL_U_L2_DATARAM_SPRAM_7_ECC_SVBUS_PEND | R/W1TS | 0h | Interrupt Pending Status for a53_dual_u_l2_dataram_spram_7_ecc_svbus_pend |
22 | A53_DUAL_U_L2_DATARAM_SPRAM_6_ECC_SVBUS_PEND | R/W1TS | 0h | Interrupt Pending Status for a53_dual_u_l2_dataram_spram_6_ecc_svbus_pend |
21 | A53_DUAL_U_L2_DATARAM_SPRAM_5_ECC_SVBUS_PEND | R/W1TS | 0h | Interrupt Pending Status for a53_dual_u_l2_dataram_spram_5_ecc_svbus_pend |
20 | A53_DUAL_U_L2_DATARAM_SPRAM_4_ECC_SVBUS_PEND | R/W1TS | 0h | Interrupt Pending Status for a53_dual_u_l2_dataram_spram_4_ecc_svbus_pend |
19 | A53_DUAL_U_L2_DATARAM_SPRAM_3_ECC_SVBUS_PEND | R/W1TS | 0h | Interrupt Pending Status for a53_dual_u_l2_dataram_spram_3_ecc_svbus_pend |
18 | A53_DUAL_U_L2_DATARAM_SPRAM_2_ECC_SVBUS_PEND | R/W1TS | 0h | Interrupt Pending Status for a53_dual_u_l2_dataram_spram_2_ecc_svbus_pend |
17 | A53_DUAL_U_L2_DATARAM_SPRAM_1_ECC_SVBUS_PEND | R/W1TS | 0h | Interrupt Pending Status for a53_dual_u_l2_dataram_spram_1_ecc_svbus_pend |
16 | A53_DUAL_U_L2_DATARAM_SPRAM_0_ECC_SVBUS_PEND | R/W1TS | 0h | Interrupt Pending Status for a53_dual_u_l2_dataram_spram_0_ecc_svbus_pend |
15 | A53_DUAL_U_L2_TAGRAM_SPRAM_WAY15_ECC_SVBUS_PEND | R/W1TS | 0h | Interrupt Pending Status for a53_dual_u_l2_tagram_spram_way15_ecc_svbus_pend |
14 | A53_DUAL_U_L2_TAGRAM_SPRAM_WAY14_ECC_SVBUS_PEND | R/W1TS | 0h | Interrupt Pending Status for a53_dual_u_l2_tagram_spram_way14_ecc_svbus_pend |
13 | A53_DUAL_U_L2_TAGRAM_SPRAM_WAY13_ECC_SVBUS_PEND | R/W1TS | 0h | Interrupt Pending Status for a53_dual_u_l2_tagram_spram_way13_ecc_svbus_pend |
12 | A53_DUAL_U_L2_TAGRAM_SPRAM_WAY12_ECC_SVBUS_PEND | R/W1TS | 0h | Interrupt Pending Status for a53_dual_u_l2_tagram_spram_way12_ecc_svbus_pend |
11 | A53_DUAL_U_L2_TAGRAM_SPRAM_WAY11_ECC_SVBUS_PEND | R/W1TS | 0h | Interrupt Pending Status for a53_dual_u_l2_tagram_spram_way11_ecc_svbus_pend |
10 | A53_DUAL_U_L2_TAGRAM_SPRAM_WAY10_ECC_SVBUS_PEND | R/W1TS | 0h | Interrupt Pending Status for a53_dual_u_l2_tagram_spram_way10_ecc_svbus_pend |
9 | A53_DUAL_U_L2_TAGRAM_SPRAM_WAY9_ECC_SVBUS_PEND | R/W1TS | 0h | Interrupt Pending Status for a53_dual_u_l2_tagram_spram_way9_ecc_svbus_pend |
8 | A53_DUAL_U_L2_TAGRAM_SPRAM_WAY8_ECC_SVBUS_PEND | R/W1TS | 0h | Interrupt Pending Status for a53_dual_u_l2_tagram_spram_way8_ecc_svbus_pend |
7 | A53_DUAL_U_L2_TAGRAM_SPRAM_WAY7_ECC_SVBUS_PEND | R/W1TS | 0h | Interrupt Pending Status for a53_dual_u_l2_tagram_spram_way7_ecc_svbus_pend |
6 | A53_DUAL_U_L2_TAGRAM_SPRAM_WAY6_ECC_SVBUS_PEND | R/W1TS | 0h | Interrupt Pending Status for a53_dual_u_l2_tagram_spram_way6_ecc_svbus_pend |
5 | A53_DUAL_U_L2_TAGRAM_SPRAM_WAY5_ECC_SVBUS_PEND | R/W1TS | 0h | Interrupt Pending Status for a53_dual_u_l2_tagram_spram_way5_ecc_svbus_pend |
4 | A53_DUAL_U_L2_TAGRAM_SPRAM_WAY4_ECC_SVBUS_PEND | R/W1TS | 0h | Interrupt Pending Status for a53_dual_u_l2_tagram_spram_way4_ecc_svbus_pend |
3 | A53_DUAL_U_L2_TAGRAM_SPRAM_WAY3_ECC_SVBUS_PEND | R/W1TS | 0h | Interrupt Pending Status for a53_dual_u_l2_tagram_spram_way3_ecc_svbus_pend |
2 | A53_DUAL_U_L2_TAGRAM_SPRAM_WAY2_ECC_SVBUS_PEND | R/W1TS | 0h | Interrupt Pending Status for a53_dual_u_l2_tagram_spram_way2_ecc_svbus_pend |
1 | A53_DUAL_U_L2_TAGRAM_SPRAM_WAY1_ECC_SVBUS_PEND | R/W1TS | 0h | Interrupt Pending Status for a53_dual_u_l2_tagram_spram_way1_ecc_svbus_pend |
0 | A53_DUAL_U_L2_TAGRAM_SPRAM_WAY0_ECC_SVBUS_PEND | R/W1TS | 0h | Interrupt Pending Status for a53_dual_u_l2_tagram_spram_way0_ecc_svbus_pend |
Short Description: Interrupt Enable Set Register 0
Long Description:
Return to Summary Table
Instance Name | Base Address |
---|---|
A53SS0 | 0071 7080h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | A53_DUAL_U_L2_DATARAM_SPRAM_7_ECC_SVBUS_ENABLE_SET | A53_DUAL_U_L2_DATARAM_SPRAM_6_ECC_SVBUS_ENABLE_SET | A53_DUAL_U_L2_DATARAM_SPRAM_5_ECC_SVBUS_ENABLE_SET | A53_DUAL_U_L2_DATARAM_SPRAM_4_ECC_SVBUS_ENABLE_SET | A53_DUAL_U_L2_DATARAM_SPRAM_3_ECC_SVBUS_ENABLE_SET | A53_DUAL_U_L2_DATARAM_SPRAM_2_ECC_SVBUS_ENABLE_SET | A53_DUAL_U_L2_DATARAM_SPRAM_1_ECC_SVBUS_ENABLE_SET | A53_DUAL_U_L2_DATARAM_SPRAM_0_ECC_SVBUS_ENABLE_SET | |||||||
NONE | R/W1TS | R/W1TS | R/W1TS | R/W1TS | R/W1TS | R/W1TS | R/W1TS | R/W1TS | |||||||
0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | ||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
A53_DUAL_U_L2_TAGRAM_SPRAM_WAY15_ECC_SVBUS_ENABLE_SET | A53_DUAL_U_L2_TAGRAM_SPRAM_WAY14_ECC_SVBUS_ENABLE_SET | A53_DUAL_U_L2_TAGRAM_SPRAM_WAY13_ECC_SVBUS_ENABLE_SET | A53_DUAL_U_L2_TAGRAM_SPRAM_WAY12_ECC_SVBUS_ENABLE_SET | A53_DUAL_U_L2_TAGRAM_SPRAM_WAY11_ECC_SVBUS_ENABLE_SET | A53_DUAL_U_L2_TAGRAM_SPRAM_WAY10_ECC_SVBUS_ENABLE_SET | A53_DUAL_U_L2_TAGRAM_SPRAM_WAY9_ECC_SVBUS_ENABLE_SET | A53_DUAL_U_L2_TAGRAM_SPRAM_WAY8_ECC_SVBUS_ENABLE_SET | A53_DUAL_U_L2_TAGRAM_SPRAM_WAY7_ECC_SVBUS_ENABLE_SET | A53_DUAL_U_L2_TAGRAM_SPRAM_WAY6_ECC_SVBUS_ENABLE_SET | A53_DUAL_U_L2_TAGRAM_SPRAM_WAY5_ECC_SVBUS_ENABLE_SET | A53_DUAL_U_L2_TAGRAM_SPRAM_WAY4_ECC_SVBUS_ENABLE_SET | A53_DUAL_U_L2_TAGRAM_SPRAM_WAY3_ECC_SVBUS_ENABLE_SET | A53_DUAL_U_L2_TAGRAM_SPRAM_WAY2_ECC_SVBUS_ENABLE_SET | A53_DUAL_U_L2_TAGRAM_SPRAM_WAY1_ECC_SVBUS_ENABLE_SET | A53_DUAL_U_L2_TAGRAM_SPRAM_WAY0_ECC_SVBUS_ENABLE_SET |
R/W1TS | R/W1TS | R/W1TS | R/W1TS | R/W1TS | R/W1TS | R/W1TS | R/W1TS | R/W1TS | R/W1TS | R/W1TS | R/W1TS | R/W1TS | R/W1TS | R/W1TS | R/W1TS |
0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
RESERVED | NONE | Reserved | ||
23 | A53_DUAL_U_L2_DATARAM_SPRAM_7_ECC_SVBUS_ENABLE_SET | R/W1TS | 0h | Interrupt Enable Set Register for a53_dual_u_l2_dataram_spram_7_ecc_svbus_pend |
22 | A53_DUAL_U_L2_DATARAM_SPRAM_6_ECC_SVBUS_ENABLE_SET | R/W1TS | 0h | Interrupt Enable Set Register for a53_dual_u_l2_dataram_spram_6_ecc_svbus_pend |
21 | A53_DUAL_U_L2_DATARAM_SPRAM_5_ECC_SVBUS_ENABLE_SET | R/W1TS | 0h | Interrupt Enable Set Register for a53_dual_u_l2_dataram_spram_5_ecc_svbus_pend |
20 | A53_DUAL_U_L2_DATARAM_SPRAM_4_ECC_SVBUS_ENABLE_SET | R/W1TS | 0h | Interrupt Enable Set Register for a53_dual_u_l2_dataram_spram_4_ecc_svbus_pend |
19 | A53_DUAL_U_L2_DATARAM_SPRAM_3_ECC_SVBUS_ENABLE_SET | R/W1TS | 0h | Interrupt Enable Set Register for a53_dual_u_l2_dataram_spram_3_ecc_svbus_pend |
18 | A53_DUAL_U_L2_DATARAM_SPRAM_2_ECC_SVBUS_ENABLE_SET | R/W1TS | 0h | Interrupt Enable Set Register for a53_dual_u_l2_dataram_spram_2_ecc_svbus_pend |
17 | A53_DUAL_U_L2_DATARAM_SPRAM_1_ECC_SVBUS_ENABLE_SET | R/W1TS | 0h | Interrupt Enable Set Register for a53_dual_u_l2_dataram_spram_1_ecc_svbus_pend |
16 | A53_DUAL_U_L2_DATARAM_SPRAM_0_ECC_SVBUS_ENABLE_SET | R/W1TS | 0h | Interrupt Enable Set Register for a53_dual_u_l2_dataram_spram_0_ecc_svbus_pend |
15 | A53_DUAL_U_L2_TAGRAM_SPRAM_WAY15_ECC_SVBUS_ENABLE_SET | R/W1TS | 0h | Interrupt Enable Set Register for a53_dual_u_l2_tagram_spram_way15_ecc_svbus_pend |
14 | A53_DUAL_U_L2_TAGRAM_SPRAM_WAY14_ECC_SVBUS_ENABLE_SET | R/W1TS | 0h | Interrupt Enable Set Register for a53_dual_u_l2_tagram_spram_way14_ecc_svbus_pend |
13 | A53_DUAL_U_L2_TAGRAM_SPRAM_WAY13_ECC_SVBUS_ENABLE_SET | R/W1TS | 0h | Interrupt Enable Set Register for a53_dual_u_l2_tagram_spram_way13_ecc_svbus_pend |
12 | A53_DUAL_U_L2_TAGRAM_SPRAM_WAY12_ECC_SVBUS_ENABLE_SET | R/W1TS | 0h | Interrupt Enable Set Register for a53_dual_u_l2_tagram_spram_way12_ecc_svbus_pend |
11 | A53_DUAL_U_L2_TAGRAM_SPRAM_WAY11_ECC_SVBUS_ENABLE_SET | R/W1TS | 0h | Interrupt Enable Set Register for a53_dual_u_l2_tagram_spram_way11_ecc_svbus_pend |
10 | A53_DUAL_U_L2_TAGRAM_SPRAM_WAY10_ECC_SVBUS_ENABLE_SET | R/W1TS | 0h | Interrupt Enable Set Register for a53_dual_u_l2_tagram_spram_way10_ecc_svbus_pend |
9 | A53_DUAL_U_L2_TAGRAM_SPRAM_WAY9_ECC_SVBUS_ENABLE_SET | R/W1TS | 0h | Interrupt Enable Set Register for a53_dual_u_l2_tagram_spram_way9_ecc_svbus_pend |
8 | A53_DUAL_U_L2_TAGRAM_SPRAM_WAY8_ECC_SVBUS_ENABLE_SET | R/W1TS | 0h | Interrupt Enable Set Register for a53_dual_u_l2_tagram_spram_way8_ecc_svbus_pend |
7 | A53_DUAL_U_L2_TAGRAM_SPRAM_WAY7_ECC_SVBUS_ENABLE_SET | R/W1TS | 0h | Interrupt Enable Set Register for a53_dual_u_l2_tagram_spram_way7_ecc_svbus_pend |
6 | A53_DUAL_U_L2_TAGRAM_SPRAM_WAY6_ECC_SVBUS_ENABLE_SET | R/W1TS | 0h | Interrupt Enable Set Register for a53_dual_u_l2_tagram_spram_way6_ecc_svbus_pend |
5 | A53_DUAL_U_L2_TAGRAM_SPRAM_WAY5_ECC_SVBUS_ENABLE_SET | R/W1TS | 0h | Interrupt Enable Set Register for a53_dual_u_l2_tagram_spram_way5_ecc_svbus_pend |
4 | A53_DUAL_U_L2_TAGRAM_SPRAM_WAY4_ECC_SVBUS_ENABLE_SET | R/W1TS | 0h | Interrupt Enable Set Register for a53_dual_u_l2_tagram_spram_way4_ecc_svbus_pend |
3 | A53_DUAL_U_L2_TAGRAM_SPRAM_WAY3_ECC_SVBUS_ENABLE_SET | R/W1TS | 0h | Interrupt Enable Set Register for a53_dual_u_l2_tagram_spram_way3_ecc_svbus_pend |
2 | A53_DUAL_U_L2_TAGRAM_SPRAM_WAY2_ECC_SVBUS_ENABLE_SET | R/W1TS | 0h | Interrupt Enable Set Register for a53_dual_u_l2_tagram_spram_way2_ecc_svbus_pend |
1 | A53_DUAL_U_L2_TAGRAM_SPRAM_WAY1_ECC_SVBUS_ENABLE_SET | R/W1TS | 0h | Interrupt Enable Set Register for a53_dual_u_l2_tagram_spram_way1_ecc_svbus_pend |
0 | A53_DUAL_U_L2_TAGRAM_SPRAM_WAY0_ECC_SVBUS_ENABLE_SET | R/W1TS | 0h | Interrupt Enable Set Register for a53_dual_u_l2_tagram_spram_way0_ecc_svbus_pend |
Short Description: Interrupt Enable Clear Register 0
Long Description:
Return to Summary Table
Instance Name | Base Address |
---|---|
A53SS0 | 0071 70C0h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | A53_DUAL_U_L2_DATARAM_SPRAM_7_ECC_SVBUS_ENABLE_CLR | A53_DUAL_U_L2_DATARAM_SPRAM_6_ECC_SVBUS_ENABLE_CLR | A53_DUAL_U_L2_DATARAM_SPRAM_5_ECC_SVBUS_ENABLE_CLR | A53_DUAL_U_L2_DATARAM_SPRAM_4_ECC_SVBUS_ENABLE_CLR | A53_DUAL_U_L2_DATARAM_SPRAM_3_ECC_SVBUS_ENABLE_CLR | A53_DUAL_U_L2_DATARAM_SPRAM_2_ECC_SVBUS_ENABLE_CLR | A53_DUAL_U_L2_DATARAM_SPRAM_1_ECC_SVBUS_ENABLE_CLR | A53_DUAL_U_L2_DATARAM_SPRAM_0_ECC_SVBUS_ENABLE_CLR | |||||||
NONE | R/W1TC | R/W1TC | R/W1TC | R/W1TC | R/W1TC | R/W1TC | R/W1TC | R/W1TC | |||||||
0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | ||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
A53_DUAL_U_L2_TAGRAM_SPRAM_WAY15_ECC_SVBUS_ENABLE_CLR | A53_DUAL_U_L2_TAGRAM_SPRAM_WAY14_ECC_SVBUS_ENABLE_CLR | A53_DUAL_U_L2_TAGRAM_SPRAM_WAY13_ECC_SVBUS_ENABLE_CLR | A53_DUAL_U_L2_TAGRAM_SPRAM_WAY12_ECC_SVBUS_ENABLE_CLR | A53_DUAL_U_L2_TAGRAM_SPRAM_WAY11_ECC_SVBUS_ENABLE_CLR | A53_DUAL_U_L2_TAGRAM_SPRAM_WAY10_ECC_SVBUS_ENABLE_CLR | A53_DUAL_U_L2_TAGRAM_SPRAM_WAY9_ECC_SVBUS_ENABLE_CLR | A53_DUAL_U_L2_TAGRAM_SPRAM_WAY8_ECC_SVBUS_ENABLE_CLR | A53_DUAL_U_L2_TAGRAM_SPRAM_WAY7_ECC_SVBUS_ENABLE_CLR | A53_DUAL_U_L2_TAGRAM_SPRAM_WAY6_ECC_SVBUS_ENABLE_CLR | A53_DUAL_U_L2_TAGRAM_SPRAM_WAY5_ECC_SVBUS_ENABLE_CLR | A53_DUAL_U_L2_TAGRAM_SPRAM_WAY4_ECC_SVBUS_ENABLE_CLR | A53_DUAL_U_L2_TAGRAM_SPRAM_WAY3_ECC_SVBUS_ENABLE_CLR | A53_DUAL_U_L2_TAGRAM_SPRAM_WAY2_ECC_SVBUS_ENABLE_CLR | A53_DUAL_U_L2_TAGRAM_SPRAM_WAY1_ECC_SVBUS_ENABLE_CLR | A53_DUAL_U_L2_TAGRAM_SPRAM_WAY0_ECC_SVBUS_ENABLE_CLR |
R/W1TC | R/W1TC | R/W1TC | R/W1TC | R/W1TC | R/W1TC | R/W1TC | R/W1TC | R/W1TC | R/W1TC | R/W1TC | R/W1TC | R/W1TC | R/W1TC | R/W1TC | R/W1TC |
0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
RESERVED | NONE | Reserved | ||
23 | A53_DUAL_U_L2_DATARAM_SPRAM_7_ECC_SVBUS_ENABLE_CLR | R/W1TC | 0h | Interrupt Enable Clear Register for a53_dual_u_l2_dataram_spram_7_ecc_svbus_pend |
22 | A53_DUAL_U_L2_DATARAM_SPRAM_6_ECC_SVBUS_ENABLE_CLR | R/W1TC | 0h | Interrupt Enable Clear Register for a53_dual_u_l2_dataram_spram_6_ecc_svbus_pend |
21 | A53_DUAL_U_L2_DATARAM_SPRAM_5_ECC_SVBUS_ENABLE_CLR | R/W1TC | 0h | Interrupt Enable Clear Register for a53_dual_u_l2_dataram_spram_5_ecc_svbus_pend |
20 | A53_DUAL_U_L2_DATARAM_SPRAM_4_ECC_SVBUS_ENABLE_CLR | R/W1TC | 0h | Interrupt Enable Clear Register for a53_dual_u_l2_dataram_spram_4_ecc_svbus_pend |
19 | A53_DUAL_U_L2_DATARAM_SPRAM_3_ECC_SVBUS_ENABLE_CLR | R/W1TC | 0h | Interrupt Enable Clear Register for a53_dual_u_l2_dataram_spram_3_ecc_svbus_pend |
18 | A53_DUAL_U_L2_DATARAM_SPRAM_2_ECC_SVBUS_ENABLE_CLR | R/W1TC | 0h | Interrupt Enable Clear Register for a53_dual_u_l2_dataram_spram_2_ecc_svbus_pend |
17 | A53_DUAL_U_L2_DATARAM_SPRAM_1_ECC_SVBUS_ENABLE_CLR | R/W1TC | 0h | Interrupt Enable Clear Register for a53_dual_u_l2_dataram_spram_1_ecc_svbus_pend |
16 | A53_DUAL_U_L2_DATARAM_SPRAM_0_ECC_SVBUS_ENABLE_CLR | R/W1TC | 0h | Interrupt Enable Clear Register for a53_dual_u_l2_dataram_spram_0_ecc_svbus_pend |
15 | A53_DUAL_U_L2_TAGRAM_SPRAM_WAY15_ECC_SVBUS_ENABLE_CLR | R/W1TC | 0h | Interrupt Enable Clear Register for a53_dual_u_l2_tagram_spram_way15_ecc_svbus_pend |
14 | A53_DUAL_U_L2_TAGRAM_SPRAM_WAY14_ECC_SVBUS_ENABLE_CLR | R/W1TC | 0h | Interrupt Enable Clear Register for a53_dual_u_l2_tagram_spram_way14_ecc_svbus_pend |
13 | A53_DUAL_U_L2_TAGRAM_SPRAM_WAY13_ECC_SVBUS_ENABLE_CLR | R/W1TC | 0h | Interrupt Enable Clear Register for a53_dual_u_l2_tagram_spram_way13_ecc_svbus_pend |
12 | A53_DUAL_U_L2_TAGRAM_SPRAM_WAY12_ECC_SVBUS_ENABLE_CLR | R/W1TC | 0h | Interrupt Enable Clear Register for a53_dual_u_l2_tagram_spram_way12_ecc_svbus_pend |
11 | A53_DUAL_U_L2_TAGRAM_SPRAM_WAY11_ECC_SVBUS_ENABLE_CLR | R/W1TC | 0h | Interrupt Enable Clear Register for a53_dual_u_l2_tagram_spram_way11_ecc_svbus_pend |
10 | A53_DUAL_U_L2_TAGRAM_SPRAM_WAY10_ECC_SVBUS_ENABLE_CLR | R/W1TC | 0h | Interrupt Enable Clear Register for a53_dual_u_l2_tagram_spram_way10_ecc_svbus_pend |
9 | A53_DUAL_U_L2_TAGRAM_SPRAM_WAY9_ECC_SVBUS_ENABLE_CLR | R/W1TC | 0h | Interrupt Enable Clear Register for a53_dual_u_l2_tagram_spram_way9_ecc_svbus_pend |
8 | A53_DUAL_U_L2_TAGRAM_SPRAM_WAY8_ECC_SVBUS_ENABLE_CLR | R/W1TC | 0h | Interrupt Enable Clear Register for a53_dual_u_l2_tagram_spram_way8_ecc_svbus_pend |
7 | A53_DUAL_U_L2_TAGRAM_SPRAM_WAY7_ECC_SVBUS_ENABLE_CLR | R/W1TC | 0h | Interrupt Enable Clear Register for a53_dual_u_l2_tagram_spram_way7_ecc_svbus_pend |
6 | A53_DUAL_U_L2_TAGRAM_SPRAM_WAY6_ECC_SVBUS_ENABLE_CLR | R/W1TC | 0h | Interrupt Enable Clear Register for a53_dual_u_l2_tagram_spram_way6_ecc_svbus_pend |
5 | A53_DUAL_U_L2_TAGRAM_SPRAM_WAY5_ECC_SVBUS_ENABLE_CLR | R/W1TC | 0h | Interrupt Enable Clear Register for a53_dual_u_l2_tagram_spram_way5_ecc_svbus_pend |
4 | A53_DUAL_U_L2_TAGRAM_SPRAM_WAY4_ECC_SVBUS_ENABLE_CLR | R/W1TC | 0h | Interrupt Enable Clear Register for a53_dual_u_l2_tagram_spram_way4_ecc_svbus_pend |
3 | A53_DUAL_U_L2_TAGRAM_SPRAM_WAY3_ECC_SVBUS_ENABLE_CLR | R/W1TC | 0h | Interrupt Enable Clear Register for a53_dual_u_l2_tagram_spram_way3_ecc_svbus_pend |
2 | A53_DUAL_U_L2_TAGRAM_SPRAM_WAY2_ECC_SVBUS_ENABLE_CLR | R/W1TC | 0h | Interrupt Enable Clear Register for a53_dual_u_l2_tagram_spram_way2_ecc_svbus_pend |
1 | A53_DUAL_U_L2_TAGRAM_SPRAM_WAY1_ECC_SVBUS_ENABLE_CLR | R/W1TC | 0h | Interrupt Enable Clear Register for a53_dual_u_l2_tagram_spram_way1_ecc_svbus_pend |
0 | A53_DUAL_U_L2_TAGRAM_SPRAM_WAY0_ECC_SVBUS_ENABLE_CLR | R/W1TC | 0h | Interrupt Enable Clear Register for a53_dual_u_l2_tagram_spram_way0_ecc_svbus_pend |
Short Description: EOI Register
Long Description:
Return to Summary Table
Instance Name | Base Address |
---|---|
A53SS0 | 0071 713Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
NONE | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | EOI_WR | ||||||||||||||
NONE | R/W1TS | ||||||||||||||
0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
RESERVED | NONE | Reserved | ||
0 | EOI_WR | R/W1TS | 0h | EOI Register |
Short Description: Interrupt Status Register 0
Long Description:
Return to Summary Table
Instance Name | Base Address |
---|---|
A53SS0 | 0071 7140h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | A53_DUAL_U_L2_DATARAM_SPRAM_7_ECC_SVBUS_PEND | A53_DUAL_U_L2_DATARAM_SPRAM_6_ECC_SVBUS_PEND | A53_DUAL_U_L2_DATARAM_SPRAM_5_ECC_SVBUS_PEND | A53_DUAL_U_L2_DATARAM_SPRAM_4_ECC_SVBUS_PEND | A53_DUAL_U_L2_DATARAM_SPRAM_3_ECC_SVBUS_PEND | A53_DUAL_U_L2_DATARAM_SPRAM_2_ECC_SVBUS_PEND | A53_DUAL_U_L2_DATARAM_SPRAM_1_ECC_SVBUS_PEND | A53_DUAL_U_L2_DATARAM_SPRAM_0_ECC_SVBUS_PEND | |||||||
NONE | R/W1TS | R/W1TS | R/W1TS | R/W1TS | R/W1TS | R/W1TS | R/W1TS | R/W1TS | |||||||
0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | ||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
A53_DUAL_U_L2_TAGRAM_SPRAM_WAY15_ECC_SVBUS_PEND | A53_DUAL_U_L2_TAGRAM_SPRAM_WAY14_ECC_SVBUS_PEND | A53_DUAL_U_L2_TAGRAM_SPRAM_WAY13_ECC_SVBUS_PEND | A53_DUAL_U_L2_TAGRAM_SPRAM_WAY12_ECC_SVBUS_PEND | A53_DUAL_U_L2_TAGRAM_SPRAM_WAY11_ECC_SVBUS_PEND | A53_DUAL_U_L2_TAGRAM_SPRAM_WAY10_ECC_SVBUS_PEND | A53_DUAL_U_L2_TAGRAM_SPRAM_WAY9_ECC_SVBUS_PEND | A53_DUAL_U_L2_TAGRAM_SPRAM_WAY8_ECC_SVBUS_PEND | A53_DUAL_U_L2_TAGRAM_SPRAM_WAY7_ECC_SVBUS_PEND | A53_DUAL_U_L2_TAGRAM_SPRAM_WAY6_ECC_SVBUS_PEND | A53_DUAL_U_L2_TAGRAM_SPRAM_WAY5_ECC_SVBUS_PEND | A53_DUAL_U_L2_TAGRAM_SPRAM_WAY4_ECC_SVBUS_PEND | A53_DUAL_U_L2_TAGRAM_SPRAM_WAY3_ECC_SVBUS_PEND | A53_DUAL_U_L2_TAGRAM_SPRAM_WAY2_ECC_SVBUS_PEND | A53_DUAL_U_L2_TAGRAM_SPRAM_WAY1_ECC_SVBUS_PEND | A53_DUAL_U_L2_TAGRAM_SPRAM_WAY0_ECC_SVBUS_PEND |
R/W1TS | R/W1TS | R/W1TS | R/W1TS | R/W1TS | R/W1TS | R/W1TS | R/W1TS | R/W1TS | R/W1TS | R/W1TS | R/W1TS | R/W1TS | R/W1TS | R/W1TS | R/W1TS |
0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
RESERVED | NONE | Reserved | ||
23 | A53_DUAL_U_L2_DATARAM_SPRAM_7_ECC_SVBUS_PEND | R/W1TS | 0h | Interrupt Pending Status for a53_dual_u_l2_dataram_spram_7_ecc_svbus_pend |
22 | A53_DUAL_U_L2_DATARAM_SPRAM_6_ECC_SVBUS_PEND | R/W1TS | 0h | Interrupt Pending Status for a53_dual_u_l2_dataram_spram_6_ecc_svbus_pend |
21 | A53_DUAL_U_L2_DATARAM_SPRAM_5_ECC_SVBUS_PEND | R/W1TS | 0h | Interrupt Pending Status for a53_dual_u_l2_dataram_spram_5_ecc_svbus_pend |
20 | A53_DUAL_U_L2_DATARAM_SPRAM_4_ECC_SVBUS_PEND | R/W1TS | 0h | Interrupt Pending Status for a53_dual_u_l2_dataram_spram_4_ecc_svbus_pend |
19 | A53_DUAL_U_L2_DATARAM_SPRAM_3_ECC_SVBUS_PEND | R/W1TS | 0h | Interrupt Pending Status for a53_dual_u_l2_dataram_spram_3_ecc_svbus_pend |
18 | A53_DUAL_U_L2_DATARAM_SPRAM_2_ECC_SVBUS_PEND | R/W1TS | 0h | Interrupt Pending Status for a53_dual_u_l2_dataram_spram_2_ecc_svbus_pend |
17 | A53_DUAL_U_L2_DATARAM_SPRAM_1_ECC_SVBUS_PEND | R/W1TS | 0h | Interrupt Pending Status for a53_dual_u_l2_dataram_spram_1_ecc_svbus_pend |
16 | A53_DUAL_U_L2_DATARAM_SPRAM_0_ECC_SVBUS_PEND | R/W1TS | 0h | Interrupt Pending Status for a53_dual_u_l2_dataram_spram_0_ecc_svbus_pend |
15 | A53_DUAL_U_L2_TAGRAM_SPRAM_WAY15_ECC_SVBUS_PEND | R/W1TS | 0h | Interrupt Pending Status for a53_dual_u_l2_tagram_spram_way15_ecc_svbus_pend |
14 | A53_DUAL_U_L2_TAGRAM_SPRAM_WAY14_ECC_SVBUS_PEND | R/W1TS | 0h | Interrupt Pending Status for a53_dual_u_l2_tagram_spram_way14_ecc_svbus_pend |
13 | A53_DUAL_U_L2_TAGRAM_SPRAM_WAY13_ECC_SVBUS_PEND | R/W1TS | 0h | Interrupt Pending Status for a53_dual_u_l2_tagram_spram_way13_ecc_svbus_pend |
12 | A53_DUAL_U_L2_TAGRAM_SPRAM_WAY12_ECC_SVBUS_PEND | R/W1TS | 0h | Interrupt Pending Status for a53_dual_u_l2_tagram_spram_way12_ecc_svbus_pend |
11 | A53_DUAL_U_L2_TAGRAM_SPRAM_WAY11_ECC_SVBUS_PEND | R/W1TS | 0h | Interrupt Pending Status for a53_dual_u_l2_tagram_spram_way11_ecc_svbus_pend |
10 | A53_DUAL_U_L2_TAGRAM_SPRAM_WAY10_ECC_SVBUS_PEND | R/W1TS | 0h | Interrupt Pending Status for a53_dual_u_l2_tagram_spram_way10_ecc_svbus_pend |
9 | A53_DUAL_U_L2_TAGRAM_SPRAM_WAY9_ECC_SVBUS_PEND | R/W1TS | 0h | Interrupt Pending Status for a53_dual_u_l2_tagram_spram_way9_ecc_svbus_pend |
8 | A53_DUAL_U_L2_TAGRAM_SPRAM_WAY8_ECC_SVBUS_PEND | R/W1TS | 0h | Interrupt Pending Status for a53_dual_u_l2_tagram_spram_way8_ecc_svbus_pend |
7 | A53_DUAL_U_L2_TAGRAM_SPRAM_WAY7_ECC_SVBUS_PEND | R/W1TS | 0h | Interrupt Pending Status for a53_dual_u_l2_tagram_spram_way7_ecc_svbus_pend |
6 | A53_DUAL_U_L2_TAGRAM_SPRAM_WAY6_ECC_SVBUS_PEND | R/W1TS | 0h | Interrupt Pending Status for a53_dual_u_l2_tagram_spram_way6_ecc_svbus_pend |
5 | A53_DUAL_U_L2_TAGRAM_SPRAM_WAY5_ECC_SVBUS_PEND | R/W1TS | 0h | Interrupt Pending Status for a53_dual_u_l2_tagram_spram_way5_ecc_svbus_pend |
4 | A53_DUAL_U_L2_TAGRAM_SPRAM_WAY4_ECC_SVBUS_PEND | R/W1TS | 0h | Interrupt Pending Status for a53_dual_u_l2_tagram_spram_way4_ecc_svbus_pend |
3 | A53_DUAL_U_L2_TAGRAM_SPRAM_WAY3_ECC_SVBUS_PEND | R/W1TS | 0h | Interrupt Pending Status for a53_dual_u_l2_tagram_spram_way3_ecc_svbus_pend |
2 | A53_DUAL_U_L2_TAGRAM_SPRAM_WAY2_ECC_SVBUS_PEND | R/W1TS | 0h | Interrupt Pending Status for a53_dual_u_l2_tagram_spram_way2_ecc_svbus_pend |
1 | A53_DUAL_U_L2_TAGRAM_SPRAM_WAY1_ECC_SVBUS_PEND | R/W1TS | 0h | Interrupt Pending Status for a53_dual_u_l2_tagram_spram_way1_ecc_svbus_pend |
0 | A53_DUAL_U_L2_TAGRAM_SPRAM_WAY0_ECC_SVBUS_PEND | R/W1TS | 0h | Interrupt Pending Status for a53_dual_u_l2_tagram_spram_way0_ecc_svbus_pend |
Short Description: Interrupt Enable Set Register 0
Long Description:
Return to Summary Table
Instance Name | Base Address |
---|---|
A53SS0 | 0071 7180h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | A53_DUAL_U_L2_DATARAM_SPRAM_7_ECC_SVBUS_ENABLE_SET | A53_DUAL_U_L2_DATARAM_SPRAM_6_ECC_SVBUS_ENABLE_SET | A53_DUAL_U_L2_DATARAM_SPRAM_5_ECC_SVBUS_ENABLE_SET | A53_DUAL_U_L2_DATARAM_SPRAM_4_ECC_SVBUS_ENABLE_SET | A53_DUAL_U_L2_DATARAM_SPRAM_3_ECC_SVBUS_ENABLE_SET | A53_DUAL_U_L2_DATARAM_SPRAM_2_ECC_SVBUS_ENABLE_SET | A53_DUAL_U_L2_DATARAM_SPRAM_1_ECC_SVBUS_ENABLE_SET | A53_DUAL_U_L2_DATARAM_SPRAM_0_ECC_SVBUS_ENABLE_SET | |||||||
NONE | R/W1TS | R/W1TS | R/W1TS | R/W1TS | R/W1TS | R/W1TS | R/W1TS | R/W1TS | |||||||
0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | ||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
A53_DUAL_U_L2_TAGRAM_SPRAM_WAY15_ECC_SVBUS_ENABLE_SET | A53_DUAL_U_L2_TAGRAM_SPRAM_WAY14_ECC_SVBUS_ENABLE_SET | A53_DUAL_U_L2_TAGRAM_SPRAM_WAY13_ECC_SVBUS_ENABLE_SET | A53_DUAL_U_L2_TAGRAM_SPRAM_WAY12_ECC_SVBUS_ENABLE_SET | A53_DUAL_U_L2_TAGRAM_SPRAM_WAY11_ECC_SVBUS_ENABLE_SET | A53_DUAL_U_L2_TAGRAM_SPRAM_WAY10_ECC_SVBUS_ENABLE_SET | A53_DUAL_U_L2_TAGRAM_SPRAM_WAY9_ECC_SVBUS_ENABLE_SET | A53_DUAL_U_L2_TAGRAM_SPRAM_WAY8_ECC_SVBUS_ENABLE_SET | A53_DUAL_U_L2_TAGRAM_SPRAM_WAY7_ECC_SVBUS_ENABLE_SET | A53_DUAL_U_L2_TAGRAM_SPRAM_WAY6_ECC_SVBUS_ENABLE_SET | A53_DUAL_U_L2_TAGRAM_SPRAM_WAY5_ECC_SVBUS_ENABLE_SET | A53_DUAL_U_L2_TAGRAM_SPRAM_WAY4_ECC_SVBUS_ENABLE_SET | A53_DUAL_U_L2_TAGRAM_SPRAM_WAY3_ECC_SVBUS_ENABLE_SET | A53_DUAL_U_L2_TAGRAM_SPRAM_WAY2_ECC_SVBUS_ENABLE_SET | A53_DUAL_U_L2_TAGRAM_SPRAM_WAY1_ECC_SVBUS_ENABLE_SET | A53_DUAL_U_L2_TAGRAM_SPRAM_WAY0_ECC_SVBUS_ENABLE_SET |
R/W1TS | R/W1TS | R/W1TS | R/W1TS | R/W1TS | R/W1TS | R/W1TS | R/W1TS | R/W1TS | R/W1TS | R/W1TS | R/W1TS | R/W1TS | R/W1TS | R/W1TS | R/W1TS |
0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
RESERVED | NONE | Reserved | ||
23 | A53_DUAL_U_L2_DATARAM_SPRAM_7_ECC_SVBUS_ENABLE_SET | R/W1TS | 0h | Interrupt Enable Set Register for a53_dual_u_l2_dataram_spram_7_ecc_svbus_pend |
22 | A53_DUAL_U_L2_DATARAM_SPRAM_6_ECC_SVBUS_ENABLE_SET | R/W1TS | 0h | Interrupt Enable Set Register for a53_dual_u_l2_dataram_spram_6_ecc_svbus_pend |
21 | A53_DUAL_U_L2_DATARAM_SPRAM_5_ECC_SVBUS_ENABLE_SET | R/W1TS | 0h | Interrupt Enable Set Register for a53_dual_u_l2_dataram_spram_5_ecc_svbus_pend |
20 | A53_DUAL_U_L2_DATARAM_SPRAM_4_ECC_SVBUS_ENABLE_SET | R/W1TS | 0h | Interrupt Enable Set Register for a53_dual_u_l2_dataram_spram_4_ecc_svbus_pend |
19 | A53_DUAL_U_L2_DATARAM_SPRAM_3_ECC_SVBUS_ENABLE_SET | R/W1TS | 0h | Interrupt Enable Set Register for a53_dual_u_l2_dataram_spram_3_ecc_svbus_pend |
18 | A53_DUAL_U_L2_DATARAM_SPRAM_2_ECC_SVBUS_ENABLE_SET | R/W1TS | 0h | Interrupt Enable Set Register for a53_dual_u_l2_dataram_spram_2_ecc_svbus_pend |
17 | A53_DUAL_U_L2_DATARAM_SPRAM_1_ECC_SVBUS_ENABLE_SET | R/W1TS | 0h | Interrupt Enable Set Register for a53_dual_u_l2_dataram_spram_1_ecc_svbus_pend |
16 | A53_DUAL_U_L2_DATARAM_SPRAM_0_ECC_SVBUS_ENABLE_SET | R/W1TS | 0h | Interrupt Enable Set Register for a53_dual_u_l2_dataram_spram_0_ecc_svbus_pend |
15 | A53_DUAL_U_L2_TAGRAM_SPRAM_WAY15_ECC_SVBUS_ENABLE_SET | R/W1TS | 0h | Interrupt Enable Set Register for a53_dual_u_l2_tagram_spram_way15_ecc_svbus_pend |
14 | A53_DUAL_U_L2_TAGRAM_SPRAM_WAY14_ECC_SVBUS_ENABLE_SET | R/W1TS | 0h | Interrupt Enable Set Register for a53_dual_u_l2_tagram_spram_way14_ecc_svbus_pend |
13 | A53_DUAL_U_L2_TAGRAM_SPRAM_WAY13_ECC_SVBUS_ENABLE_SET | R/W1TS | 0h | Interrupt Enable Set Register for a53_dual_u_l2_tagram_spram_way13_ecc_svbus_pend |
12 | A53_DUAL_U_L2_TAGRAM_SPRAM_WAY12_ECC_SVBUS_ENABLE_SET | R/W1TS | 0h | Interrupt Enable Set Register for a53_dual_u_l2_tagram_spram_way12_ecc_svbus_pend |
11 | A53_DUAL_U_L2_TAGRAM_SPRAM_WAY11_ECC_SVBUS_ENABLE_SET | R/W1TS | 0h | Interrupt Enable Set Register for a53_dual_u_l2_tagram_spram_way11_ecc_svbus_pend |
10 | A53_DUAL_U_L2_TAGRAM_SPRAM_WAY10_ECC_SVBUS_ENABLE_SET | R/W1TS | 0h | Interrupt Enable Set Register for a53_dual_u_l2_tagram_spram_way10_ecc_svbus_pend |
9 | A53_DUAL_U_L2_TAGRAM_SPRAM_WAY9_ECC_SVBUS_ENABLE_SET | R/W1TS | 0h | Interrupt Enable Set Register for a53_dual_u_l2_tagram_spram_way9_ecc_svbus_pend |
8 | A53_DUAL_U_L2_TAGRAM_SPRAM_WAY8_ECC_SVBUS_ENABLE_SET | R/W1TS | 0h | Interrupt Enable Set Register for a53_dual_u_l2_tagram_spram_way8_ecc_svbus_pend |
7 | A53_DUAL_U_L2_TAGRAM_SPRAM_WAY7_ECC_SVBUS_ENABLE_SET | R/W1TS | 0h | Interrupt Enable Set Register for a53_dual_u_l2_tagram_spram_way7_ecc_svbus_pend |
6 | A53_DUAL_U_L2_TAGRAM_SPRAM_WAY6_ECC_SVBUS_ENABLE_SET | R/W1TS | 0h | Interrupt Enable Set Register for a53_dual_u_l2_tagram_spram_way6_ecc_svbus_pend |
5 | A53_DUAL_U_L2_TAGRAM_SPRAM_WAY5_ECC_SVBUS_ENABLE_SET | R/W1TS | 0h | Interrupt Enable Set Register for a53_dual_u_l2_tagram_spram_way5_ecc_svbus_pend |
4 | A53_DUAL_U_L2_TAGRAM_SPRAM_WAY4_ECC_SVBUS_ENABLE_SET | R/W1TS | 0h | Interrupt Enable Set Register for a53_dual_u_l2_tagram_spram_way4_ecc_svbus_pend |
3 | A53_DUAL_U_L2_TAGRAM_SPRAM_WAY3_ECC_SVBUS_ENABLE_SET | R/W1TS | 0h | Interrupt Enable Set Register for a53_dual_u_l2_tagram_spram_way3_ecc_svbus_pend |
2 | A53_DUAL_U_L2_TAGRAM_SPRAM_WAY2_ECC_SVBUS_ENABLE_SET | R/W1TS | 0h | Interrupt Enable Set Register for a53_dual_u_l2_tagram_spram_way2_ecc_svbus_pend |
1 | A53_DUAL_U_L2_TAGRAM_SPRAM_WAY1_ECC_SVBUS_ENABLE_SET | R/W1TS | 0h | Interrupt Enable Set Register for a53_dual_u_l2_tagram_spram_way1_ecc_svbus_pend |
0 | A53_DUAL_U_L2_TAGRAM_SPRAM_WAY0_ECC_SVBUS_ENABLE_SET | R/W1TS | 0h | Interrupt Enable Set Register for a53_dual_u_l2_tagram_spram_way0_ecc_svbus_pend |
Short Description: Interrupt Enable Clear Register 0
Long Description:
Return to Summary Table
Instance Name | Base Address |
---|---|
A53SS0 | 0071 71C0h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | A53_DUAL_U_L2_DATARAM_SPRAM_7_ECC_SVBUS_ENABLE_CLR | A53_DUAL_U_L2_DATARAM_SPRAM_6_ECC_SVBUS_ENABLE_CLR | A53_DUAL_U_L2_DATARAM_SPRAM_5_ECC_SVBUS_ENABLE_CLR | A53_DUAL_U_L2_DATARAM_SPRAM_4_ECC_SVBUS_ENABLE_CLR | A53_DUAL_U_L2_DATARAM_SPRAM_3_ECC_SVBUS_ENABLE_CLR | A53_DUAL_U_L2_DATARAM_SPRAM_2_ECC_SVBUS_ENABLE_CLR | A53_DUAL_U_L2_DATARAM_SPRAM_1_ECC_SVBUS_ENABLE_CLR | A53_DUAL_U_L2_DATARAM_SPRAM_0_ECC_SVBUS_ENABLE_CLR | |||||||
NONE | R/W1TC | R/W1TC | R/W1TC | R/W1TC | R/W1TC | R/W1TC | R/W1TC | R/W1TC | |||||||
0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | ||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
A53_DUAL_U_L2_TAGRAM_SPRAM_WAY15_ECC_SVBUS_ENABLE_CLR | A53_DUAL_U_L2_TAGRAM_SPRAM_WAY14_ECC_SVBUS_ENABLE_CLR | A53_DUAL_U_L2_TAGRAM_SPRAM_WAY13_ECC_SVBUS_ENABLE_CLR | A53_DUAL_U_L2_TAGRAM_SPRAM_WAY12_ECC_SVBUS_ENABLE_CLR | A53_DUAL_U_L2_TAGRAM_SPRAM_WAY11_ECC_SVBUS_ENABLE_CLR | A53_DUAL_U_L2_TAGRAM_SPRAM_WAY10_ECC_SVBUS_ENABLE_CLR | A53_DUAL_U_L2_TAGRAM_SPRAM_WAY9_ECC_SVBUS_ENABLE_CLR | A53_DUAL_U_L2_TAGRAM_SPRAM_WAY8_ECC_SVBUS_ENABLE_CLR | A53_DUAL_U_L2_TAGRAM_SPRAM_WAY7_ECC_SVBUS_ENABLE_CLR | A53_DUAL_U_L2_TAGRAM_SPRAM_WAY6_ECC_SVBUS_ENABLE_CLR | A53_DUAL_U_L2_TAGRAM_SPRAM_WAY5_ECC_SVBUS_ENABLE_CLR | A53_DUAL_U_L2_TAGRAM_SPRAM_WAY4_ECC_SVBUS_ENABLE_CLR | A53_DUAL_U_L2_TAGRAM_SPRAM_WAY3_ECC_SVBUS_ENABLE_CLR | A53_DUAL_U_L2_TAGRAM_SPRAM_WAY2_ECC_SVBUS_ENABLE_CLR | A53_DUAL_U_L2_TAGRAM_SPRAM_WAY1_ECC_SVBUS_ENABLE_CLR | A53_DUAL_U_L2_TAGRAM_SPRAM_WAY0_ECC_SVBUS_ENABLE_CLR |
R/W1TC | R/W1TC | R/W1TC | R/W1TC | R/W1TC | R/W1TC | R/W1TC | R/W1TC | R/W1TC | R/W1TC | R/W1TC | R/W1TC | R/W1TC | R/W1TC | R/W1TC | R/W1TC |
0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
RESERVED | NONE | Reserved | ||
23 | A53_DUAL_U_L2_DATARAM_SPRAM_7_ECC_SVBUS_ENABLE_CLR | R/W1TC | 0h | Interrupt Enable Clear Register for a53_dual_u_l2_dataram_spram_7_ecc_svbus_pend |
22 | A53_DUAL_U_L2_DATARAM_SPRAM_6_ECC_SVBUS_ENABLE_CLR | R/W1TC | 0h | Interrupt Enable Clear Register for a53_dual_u_l2_dataram_spram_6_ecc_svbus_pend |
21 | A53_DUAL_U_L2_DATARAM_SPRAM_5_ECC_SVBUS_ENABLE_CLR | R/W1TC | 0h | Interrupt Enable Clear Register for a53_dual_u_l2_dataram_spram_5_ecc_svbus_pend |
20 | A53_DUAL_U_L2_DATARAM_SPRAM_4_ECC_SVBUS_ENABLE_CLR | R/W1TC | 0h | Interrupt Enable Clear Register for a53_dual_u_l2_dataram_spram_4_ecc_svbus_pend |
19 | A53_DUAL_U_L2_DATARAM_SPRAM_3_ECC_SVBUS_ENABLE_CLR | R/W1TC | 0h | Interrupt Enable Clear Register for a53_dual_u_l2_dataram_spram_3_ecc_svbus_pend |
18 | A53_DUAL_U_L2_DATARAM_SPRAM_2_ECC_SVBUS_ENABLE_CLR | R/W1TC | 0h | Interrupt Enable Clear Register for a53_dual_u_l2_dataram_spram_2_ecc_svbus_pend |
17 | A53_DUAL_U_L2_DATARAM_SPRAM_1_ECC_SVBUS_ENABLE_CLR | R/W1TC | 0h | Interrupt Enable Clear Register for a53_dual_u_l2_dataram_spram_1_ecc_svbus_pend |
16 | A53_DUAL_U_L2_DATARAM_SPRAM_0_ECC_SVBUS_ENABLE_CLR | R/W1TC | 0h | Interrupt Enable Clear Register for a53_dual_u_l2_dataram_spram_0_ecc_svbus_pend |
15 | A53_DUAL_U_L2_TAGRAM_SPRAM_WAY15_ECC_SVBUS_ENABLE_CLR | R/W1TC | 0h | Interrupt Enable Clear Register for a53_dual_u_l2_tagram_spram_way15_ecc_svbus_pend |
14 | A53_DUAL_U_L2_TAGRAM_SPRAM_WAY14_ECC_SVBUS_ENABLE_CLR | R/W1TC | 0h | Interrupt Enable Clear Register for a53_dual_u_l2_tagram_spram_way14_ecc_svbus_pend |
13 | A53_DUAL_U_L2_TAGRAM_SPRAM_WAY13_ECC_SVBUS_ENABLE_CLR | R/W1TC | 0h | Interrupt Enable Clear Register for a53_dual_u_l2_tagram_spram_way13_ecc_svbus_pend |
12 | A53_DUAL_U_L2_TAGRAM_SPRAM_WAY12_ECC_SVBUS_ENABLE_CLR | R/W1TC | 0h | Interrupt Enable Clear Register for a53_dual_u_l2_tagram_spram_way12_ecc_svbus_pend |
11 | A53_DUAL_U_L2_TAGRAM_SPRAM_WAY11_ECC_SVBUS_ENABLE_CLR | R/W1TC | 0h | Interrupt Enable Clear Register for a53_dual_u_l2_tagram_spram_way11_ecc_svbus_pend |
10 | A53_DUAL_U_L2_TAGRAM_SPRAM_WAY10_ECC_SVBUS_ENABLE_CLR | R/W1TC | 0h | Interrupt Enable Clear Register for a53_dual_u_l2_tagram_spram_way10_ecc_svbus_pend |
9 | A53_DUAL_U_L2_TAGRAM_SPRAM_WAY9_ECC_SVBUS_ENABLE_CLR | R/W1TC | 0h | Interrupt Enable Clear Register for a53_dual_u_l2_tagram_spram_way9_ecc_svbus_pend |
8 | A53_DUAL_U_L2_TAGRAM_SPRAM_WAY8_ECC_SVBUS_ENABLE_CLR | R/W1TC | 0h | Interrupt Enable Clear Register for a53_dual_u_l2_tagram_spram_way8_ecc_svbus_pend |
7 | A53_DUAL_U_L2_TAGRAM_SPRAM_WAY7_ECC_SVBUS_ENABLE_CLR | R/W1TC | 0h | Interrupt Enable Clear Register for a53_dual_u_l2_tagram_spram_way7_ecc_svbus_pend |
6 | A53_DUAL_U_L2_TAGRAM_SPRAM_WAY6_ECC_SVBUS_ENABLE_CLR | R/W1TC | 0h | Interrupt Enable Clear Register for a53_dual_u_l2_tagram_spram_way6_ecc_svbus_pend |
5 | A53_DUAL_U_L2_TAGRAM_SPRAM_WAY5_ECC_SVBUS_ENABLE_CLR | R/W1TC | 0h | Interrupt Enable Clear Register for a53_dual_u_l2_tagram_spram_way5_ecc_svbus_pend |
4 | A53_DUAL_U_L2_TAGRAM_SPRAM_WAY4_ECC_SVBUS_ENABLE_CLR | R/W1TC | 0h | Interrupt Enable Clear Register for a53_dual_u_l2_tagram_spram_way4_ecc_svbus_pend |
3 | A53_DUAL_U_L2_TAGRAM_SPRAM_WAY3_ECC_SVBUS_ENABLE_CLR | R/W1TC | 0h | Interrupt Enable Clear Register for a53_dual_u_l2_tagram_spram_way3_ecc_svbus_pend |
2 | A53_DUAL_U_L2_TAGRAM_SPRAM_WAY2_ECC_SVBUS_ENABLE_CLR | R/W1TC | 0h | Interrupt Enable Clear Register for a53_dual_u_l2_tagram_spram_way2_ecc_svbus_pend |
1 | A53_DUAL_U_L2_TAGRAM_SPRAM_WAY1_ECC_SVBUS_ENABLE_CLR | R/W1TC | 0h | Interrupt Enable Clear Register for a53_dual_u_l2_tagram_spram_way1_ecc_svbus_pend |
0 | A53_DUAL_U_L2_TAGRAM_SPRAM_WAY0_ECC_SVBUS_ENABLE_CLR | R/W1TC | 0h | Interrupt Enable Clear Register for a53_dual_u_l2_tagram_spram_way0_ecc_svbus_pend |
Short Description: AGGR interrupt enable set Register
Long Description:
Return to Summary Table
Instance Name | Base Address |
---|---|
A53SS0 | 0071 7200h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
NONE | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | TIMEOUT | PARITY | |||||||||||||
NONE | R/W1TS | R/W1TS | |||||||||||||
0 | 0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
RESERVED | NONE | Reserved | ||
1 | TIMEOUT | R/W1TS | 0h | interrupt enable set for svbus timeout errors |
0 | PARITY | R/W1TS | 0h | interrupt enable set for parity errors |
Short Description: AGGR interrupt enable clear Register
Long Description:
Return to Summary Table
Instance Name | Base Address |
---|---|
A53SS0 | 0071 7204h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
NONE | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | TIMEOUT | PARITY | |||||||||||||
NONE | R/W1TC | R/W1TC | |||||||||||||
0 | 0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
RESERVED | NONE | Reserved | ||
1 | TIMEOUT | R/W1TC | 0h | interrupt enable clear for svbus timeout errors |
0 | PARITY | R/W1TC | 0h | interrupt enable clear for parity errors |
Short Description: AGGR interrupt status set Register
Long Description:
Return to Summary Table
Instance Name | Base Address |
---|---|
A53SS0 | 0071 7208h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
NONE | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | TIMEOUT | PARITY | |||||||||||||
NONE | R/WI | R/WI | |||||||||||||
0 | 0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
RESERVED | NONE | Reserved | ||
3 - 2 | TIMEOUT | R/WI | 0h | interrupt status set for svbus timeout errors |
1 - 0 | PARITY | R/WI | 0h | interrupt status set for parity errors |
Short Description: AGGR interrupt status clear Register
Long Description:
Return to Summary Table
Instance Name | Base Address |
---|---|
A53SS0 | 0071 720Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
NONE | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | TIMEOUT | PARITY | |||||||||||||
NONE | R/WD | R/WD | |||||||||||||
0 | 0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
RESERVED | NONE | Reserved | ||
3 - 2 | TIMEOUT | R/WD | 0h | interrupt status clear for svbus timeout errors |
1 - 0 | PARITY | R/WD | 0h | interrupt status clear for parity errors |
Short Description: Aggregator Revision Register
Long Description:
Return to Summary Table
Instance Name | Base Address |
---|---|
A53SS0 | 0071 7400h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
SCHEME | BU | MODULE_ID | |||||||||||||
R | R | R | |||||||||||||
1 | 10 | 11010100000 | |||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
REVRTL | REVMAJ | CUSTOM | REVMIN | ||||||||||||
R | R | R | R | ||||||||||||
101 | 10 | 0 | 1 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 - 30 | SCHEME | R | 1h | Scheme |
29 - 28 | BU | R | 2h | bu |
27 - 16 | MODULE_ID | R | 6A0h | Module ID |
15 - 11 | REVRTL | R | 5h | RTL version |
10 - 8 | REVMAJ | R | 2h | Major version |
7 - 6 | CUSTOM | R | 0h | Custom version |
5 - 0 | REVMIN | R | 1h | Minor version |
Short Description: ECC Vector Register
Long Description:
Return to Summary Table
Instance Name | Base Address |
---|---|
A53SS0 | 0071 7408h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | RD_SVBUS_DONE | RD_SVBUS_ADDRESS | |||||||||||||
NONE | R/W1TC | R/W | |||||||||||||
0 | 0 | ||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RD_SVBUS | RESERVED | ECC_VECTOR | |||||||||||||
R/W1TS | NONE | R/W | |||||||||||||
0 | 0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
RESERVED | NONE | Reserved | ||
24 | RD_SVBUS_DONE | R/W1TC | 0h | Status to indicate if read on serial VBUS is complete, write of any value will clear this bit. |
23 - 16 | RD_SVBUS_ADDRESS | R/W | 0h | Read address |
15 | RD_SVBUS | R/W1TS | 0h | Write 1 to trigger a read on the serial VBUS |
RESERVED | NONE | Reserved | ||
10 - 0 | ECC_VECTOR | R/W | 0h | Value written to select the corresponding ECC RAM for control or status |
Short Description: Misc Status
Long Description:
Return to Summary Table
Instance Name | Base Address |
---|---|
A53SS0 | 0071 740Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
NONE | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | NUM_RAMS | ||||||||||||||
NONE | R | ||||||||||||||
11011 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
RESERVED | NONE | Reserved | ||
10 - 0 | NUM_RAMS | R | 1Bh | Indicates the number of RAMS serviced by the ECC aggregator |
Short Description: Reserved Area for Serial VBUS Registers
Long Description:
Return to Summary Table
Instance Name | Base Address |
---|---|
A53SS0 | 0071 7410h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
DATA | |||||||||||||||
R/W | |||||||||||||||
0 | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DATA | |||||||||||||||
R/W | |||||||||||||||
0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 - 0 | DATA | R/W | 0h | Serial VBUS register data |
Short Description: EOI Register
Long Description:
Return to Summary Table
Instance Name | Base Address |
---|---|
A53SS0 | 0071 743Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
NONE | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | EOI_WR | ||||||||||||||
NONE | R/W1TS | ||||||||||||||
0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
RESERVED | NONE | Reserved | ||
0 | EOI_WR | R/W1TS | 0h | EOI Register |
Short Description: Interrupt Status Register 0
Long Description:
Return to Summary Table
Instance Name | Base Address |
---|---|
A53SS0 | 0071 7440h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | CPU0_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY3_ECC_SVBUS_PEND | CPU0_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY2_ECC_SVBUS_PEND | CPU0_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY1_ECC_SVBUS_PEND | CPU0_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY0_ECC_SVBUS_PEND | CPU0_A53_DUAL_U_TLB_SPRAM_BANK3_ECC_SVBUS_PEND | CPU0_A53_DUAL_U_TLB_SPRAM_BANK2_ECC_SVBUS_PEND | CPU0_A53_DUAL_U_TLB_SPRAM_BANK1_ECC_SVBUS_PEND | CPU0_A53_DUAL_U_TLB_SPRAM_BANK0_ECC_SVBUS_PEND | CPU0_A53_DUAL_U_DDIRTY_SPRAM_ECC_SVBUS_PEND | CPU0_A53_DUAL_U_DTAG_SPRAM_BANK3_ECC_SVBUS_PEND | CPU0_A53_DUAL_U_DTAG_SPRAM_BANK2_ECC_SVBUS_PEND | ||||
NONE | R/W1TS | R/W1TS | R/W1TS | R/W1TS | R/W1TS | R/W1TS | R/W1TS | R/W1TS | R/W1TS | R/W1TS | R/W1TS | ||||
0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CPU0_A53_DUAL_U_DTAG_SPRAM_BANK1_ECC_SVBUS_PEND | CPU0_A53_DUAL_U_DTAG_SPRAM_BANK0_ECC_SVBUS_PEND | CPU0_A53_DUAL_U_DDATA_SPRAM_BANK7_ECC_SVBUS_PEND | CPU0_A53_DUAL_U_DDATA_SPRAM_BANK6_ECC_SVBUS_PEND | CPU0_A53_DUAL_U_DDATA_SPRAM_BANK5_ECC_SVBUS_PEND | CPU0_A53_DUAL_U_DDATA_SPRAM_BANK4_ECC_SVBUS_PEND | CPU0_A53_DUAL_U_DDATA_SPRAM_BANK3_ECC_SVBUS_PEND | CPU0_A53_DUAL_U_DDATA_SPRAM_BANK2_ECC_SVBUS_PEND | CPU0_A53_DUAL_U_DDATA_SPRAM_BANK1_ECC_SVBUS_PEND | CPU0_A53_DUAL_U_DDATA_SPRAM_BANK0_ECC_SVBUS_PEND | CPU0_A53_DUAL_U_ITAG_SPRAM_RAM1_ECC_SVBUS_PEND | CPU0_A53_DUAL_U_ITAG_SPRAM_RAM0_ECC_SVBUS_PEND | CPU0_A53_DUAL_U_IDATA_SPRAM_BANK1_HI_ECC_SVBUS_PEND | CPU0_A53_DUAL_U_IDATA_SPRAM_BANK1_LO_ECC_SVBUS_PEND | CPU0_A53_DUAL_U_IDATA_SPRAM_BANK0_HI_ECC_SVBUS_PEND | CPU0_A53_DUAL_U_IDATA_SPRAM_BANK0_LO_ECC_SVBUS_PEND |
R/W1TS | R/W1TS | R/W1TS | R/W1TS | R/W1TS | R/W1TS | R/W1TS | R/W1TS | R/W1TS | R/W1TS | R/W1TS | R/W1TS | R/W1TS | R/W1TS | R/W1TS | R/W1TS |
0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
RESERVED | NONE | Reserved | ||
26 | CPU0_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY3_ECC_SVBUS_PEND | R/W1TS | 0h | Interrupt Pending Status for cpu0_a53_dual_u_l1d_tagram_spram_way3_ecc_svbus_pend |
25 | CPU0_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY2_ECC_SVBUS_PEND | R/W1TS | 0h | Interrupt Pending Status for cpu0_a53_dual_u_l1d_tagram_spram_way2_ecc_svbus_pend |
24 | CPU0_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY1_ECC_SVBUS_PEND | R/W1TS | 0h | Interrupt Pending Status for cpu0_a53_dual_u_l1d_tagram_spram_way1_ecc_svbus_pend |
23 | CPU0_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY0_ECC_SVBUS_PEND | R/W1TS | 0h | Interrupt Pending Status for cpu0_a53_dual_u_l1d_tagram_spram_way0_ecc_svbus_pend |
22 | CPU0_A53_DUAL_U_TLB_SPRAM_BANK3_ECC_SVBUS_PEND | R/W1TS | 0h | Interrupt Pending Status for cpu0_a53_dual_u_tlb_spram_bank3_ecc_svbus_pend |
21 | CPU0_A53_DUAL_U_TLB_SPRAM_BANK2_ECC_SVBUS_PEND | R/W1TS | 0h | Interrupt Pending Status for cpu0_a53_dual_u_tlb_spram_bank2_ecc_svbus_pend |
20 | CPU0_A53_DUAL_U_TLB_SPRAM_BANK1_ECC_SVBUS_PEND | R/W1TS | 0h | Interrupt Pending Status for cpu0_a53_dual_u_tlb_spram_bank1_ecc_svbus_pend |
19 | CPU0_A53_DUAL_U_TLB_SPRAM_BANK0_ECC_SVBUS_PEND | R/W1TS | 0h | Interrupt Pending Status for cpu0_a53_dual_u_tlb_spram_bank0_ecc_svbus_pend |
18 | CPU0_A53_DUAL_U_DDIRTY_SPRAM_ECC_SVBUS_PEND | R/W1TS | 0h | Interrupt Pending Status for cpu0_a53_dual_u_ddirty_spram_ecc_svbus_pend |
17 | CPU0_A53_DUAL_U_DTAG_SPRAM_BANK3_ECC_SVBUS_PEND | R/W1TS | 0h | Interrupt Pending Status for cpu0_a53_dual_u_dtag_spram_bank3_ecc_svbus_pend |
16 | CPU0_A53_DUAL_U_DTAG_SPRAM_BANK2_ECC_SVBUS_PEND | R/W1TS | 0h | Interrupt Pending Status for cpu0_a53_dual_u_dtag_spram_bank2_ecc_svbus_pend |
15 | CPU0_A53_DUAL_U_DTAG_SPRAM_BANK1_ECC_SVBUS_PEND | R/W1TS | 0h | Interrupt Pending Status for cpu0_a53_dual_u_dtag_spram_bank1_ecc_svbus_pend |
14 | CPU0_A53_DUAL_U_DTAG_SPRAM_BANK0_ECC_SVBUS_PEND | R/W1TS | 0h | Interrupt Pending Status for cpu0_a53_dual_u_dtag_spram_bank0_ecc_svbus_pend |
13 | CPU0_A53_DUAL_U_DDATA_SPRAM_BANK7_ECC_SVBUS_PEND | R/W1TS | 0h | Interrupt Pending Status for cpu0_a53_dual_u_ddata_spram_bank7_ecc_svbus_pend |
12 | CPU0_A53_DUAL_U_DDATA_SPRAM_BANK6_ECC_SVBUS_PEND | R/W1TS | 0h | Interrupt Pending Status for cpu0_a53_dual_u_ddata_spram_bank6_ecc_svbus_pend |
11 | CPU0_A53_DUAL_U_DDATA_SPRAM_BANK5_ECC_SVBUS_PEND | R/W1TS | 0h | Interrupt Pending Status for cpu0_a53_dual_u_ddata_spram_bank5_ecc_svbus_pend |
10 | CPU0_A53_DUAL_U_DDATA_SPRAM_BANK4_ECC_SVBUS_PEND | R/W1TS | 0h | Interrupt Pending Status for cpu0_a53_dual_u_ddata_spram_bank4_ecc_svbus_pend |
9 | CPU0_A53_DUAL_U_DDATA_SPRAM_BANK3_ECC_SVBUS_PEND | R/W1TS | 0h | Interrupt Pending Status for cpu0_a53_dual_u_ddata_spram_bank3_ecc_svbus_pend |
8 | CPU0_A53_DUAL_U_DDATA_SPRAM_BANK2_ECC_SVBUS_PEND | R/W1TS | 0h | Interrupt Pending Status for cpu0_a53_dual_u_ddata_spram_bank2_ecc_svbus_pend |
7 | CPU0_A53_DUAL_U_DDATA_SPRAM_BANK1_ECC_SVBUS_PEND | R/W1TS | 0h | Interrupt Pending Status for cpu0_a53_dual_u_ddata_spram_bank1_ecc_svbus_pend |
6 | CPU0_A53_DUAL_U_DDATA_SPRAM_BANK0_ECC_SVBUS_PEND | R/W1TS | 0h | Interrupt Pending Status for cpu0_a53_dual_u_ddata_spram_bank0_ecc_svbus_pend |
5 | CPU0_A53_DUAL_U_ITAG_SPRAM_RAM1_ECC_SVBUS_PEND | R/W1TS | 0h | Interrupt Pending Status for cpu0_a53_dual_u_itag_spram_ram1_ecc_svbus_pend |
4 | CPU0_A53_DUAL_U_ITAG_SPRAM_RAM0_ECC_SVBUS_PEND | R/W1TS | 0h | Interrupt Pending Status for cpu0_a53_dual_u_itag_spram_ram0_ecc_svbus_pend |
3 | CPU0_A53_DUAL_U_IDATA_SPRAM_BANK1_HI_ECC_SVBUS_PEND | R/W1TS | 0h | Interrupt Pending Status for cpu0_a53_dual_u_idata_spram_bank1_hi_ecc_svbus_pend |
2 | CPU0_A53_DUAL_U_IDATA_SPRAM_BANK1_LO_ECC_SVBUS_PEND | R/W1TS | 0h | Interrupt Pending Status for cpu0_a53_dual_u_idata_spram_bank1_lo_ecc_svbus_pend |
1 | CPU0_A53_DUAL_U_IDATA_SPRAM_BANK0_HI_ECC_SVBUS_PEND | R/W1TS | 0h | Interrupt Pending Status for cpu0_a53_dual_u_idata_spram_bank0_hi_ecc_svbus_pend |
0 | CPU0_A53_DUAL_U_IDATA_SPRAM_BANK0_LO_ECC_SVBUS_PEND | R/W1TS | 0h | Interrupt Pending Status for cpu0_a53_dual_u_idata_spram_bank0_lo_ecc_svbus_pend |
Short Description: Interrupt Enable Set Register 0
Long Description:
Return to Summary Table
Instance Name | Base Address |
---|---|
A53SS0 | 0071 7480h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | CPU0_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY3_ECC_SVBUS_ENABLE_SET | CPU0_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY2_ECC_SVBUS_ENABLE_SET | CPU0_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY1_ECC_SVBUS_ENABLE_SET | CPU0_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY0_ECC_SVBUS_ENABLE_SET | CPU0_A53_DUAL_U_TLB_SPRAM_BANK3_ECC_SVBUS_ENABLE_SET | CPU0_A53_DUAL_U_TLB_SPRAM_BANK2_ECC_SVBUS_ENABLE_SET | CPU0_A53_DUAL_U_TLB_SPRAM_BANK1_ECC_SVBUS_ENABLE_SET | CPU0_A53_DUAL_U_TLB_SPRAM_BANK0_ECC_SVBUS_ENABLE_SET | CPU0_A53_DUAL_U_DDIRTY_SPRAM_ECC_SVBUS_ENABLE_SET | CPU0_A53_DUAL_U_DTAG_SPRAM_BANK3_ECC_SVBUS_ENABLE_SET | CPU0_A53_DUAL_U_DTAG_SPRAM_BANK2_ECC_SVBUS_ENABLE_SET | ||||
NONE | R/W1TS | R/W1TS | R/W1TS | R/W1TS | R/W1TS | R/W1TS | R/W1TS | R/W1TS | R/W1TS | R/W1TS | R/W1TS | ||||
0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CPU0_A53_DUAL_U_DTAG_SPRAM_BANK1_ECC_SVBUS_ENABLE_SET | CPU0_A53_DUAL_U_DTAG_SPRAM_BANK0_ECC_SVBUS_ENABLE_SET | CPU0_A53_DUAL_U_DDATA_SPRAM_BANK7_ECC_SVBUS_ENABLE_SET | CPU0_A53_DUAL_U_DDATA_SPRAM_BANK6_ECC_SVBUS_ENABLE_SET | CPU0_A53_DUAL_U_DDATA_SPRAM_BANK5_ECC_SVBUS_ENABLE_SET | CPU0_A53_DUAL_U_DDATA_SPRAM_BANK4_ECC_SVBUS_ENABLE_SET | CPU0_A53_DUAL_U_DDATA_SPRAM_BANK3_ECC_SVBUS_ENABLE_SET | CPU0_A53_DUAL_U_DDATA_SPRAM_BANK2_ECC_SVBUS_ENABLE_SET | CPU0_A53_DUAL_U_DDATA_SPRAM_BANK1_ECC_SVBUS_ENABLE_SET | CPU0_A53_DUAL_U_DDATA_SPRAM_BANK0_ECC_SVBUS_ENABLE_SET | CPU0_A53_DUAL_U_ITAG_SPRAM_RAM1_ECC_SVBUS_ENABLE_SET | CPU0_A53_DUAL_U_ITAG_SPRAM_RAM0_ECC_SVBUS_ENABLE_SET | CPU0_A53_DUAL_U_IDATA_SPRAM_BANK1_HI_ECC_SVBUS_ENABLE_SET | CPU0_A53_DUAL_U_IDATA_SPRAM_BANK1_LO_ECC_SVBUS_ENABLE_SET | CPU0_A53_DUAL_U_IDATA_SPRAM_BANK0_HI_ECC_SVBUS_ENABLE_SET | CPU0_A53_DUAL_U_IDATA_SPRAM_BANK0_LO_ECC_SVBUS_ENABLE_SET |
R/W1TS | R/W1TS | R/W1TS | R/W1TS | R/W1TS | R/W1TS | R/W1TS | R/W1TS | R/W1TS | R/W1TS | R/W1TS | R/W1TS | R/W1TS | R/W1TS | R/W1TS | R/W1TS |
0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
RESERVED | NONE | Reserved | ||
26 | CPU0_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY3_ECC_SVBUS_ENABLE_SET | R/W1TS | 0h | Interrupt Enable Set Register for cpu0_a53_dual_u_l1d_tagram_spram_way3_ecc_svbus_pend |
25 | CPU0_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY2_ECC_SVBUS_ENABLE_SET | R/W1TS | 0h | Interrupt Enable Set Register for cpu0_a53_dual_u_l1d_tagram_spram_way2_ecc_svbus_pend |
24 | CPU0_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY1_ECC_SVBUS_ENABLE_SET | R/W1TS | 0h | Interrupt Enable Set Register for cpu0_a53_dual_u_l1d_tagram_spram_way1_ecc_svbus_pend |
23 | CPU0_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY0_ECC_SVBUS_ENABLE_SET | R/W1TS | 0h | Interrupt Enable Set Register for cpu0_a53_dual_u_l1d_tagram_spram_way0_ecc_svbus_pend |
22 | CPU0_A53_DUAL_U_TLB_SPRAM_BANK3_ECC_SVBUS_ENABLE_SET | R/W1TS | 0h | Interrupt Enable Set Register for cpu0_a53_dual_u_tlb_spram_bank3_ecc_svbus_pend |
21 | CPU0_A53_DUAL_U_TLB_SPRAM_BANK2_ECC_SVBUS_ENABLE_SET | R/W1TS | 0h | Interrupt Enable Set Register for cpu0_a53_dual_u_tlb_spram_bank2_ecc_svbus_pend |
20 | CPU0_A53_DUAL_U_TLB_SPRAM_BANK1_ECC_SVBUS_ENABLE_SET | R/W1TS | 0h | Interrupt Enable Set Register for cpu0_a53_dual_u_tlb_spram_bank1_ecc_svbus_pend |
19 | CPU0_A53_DUAL_U_TLB_SPRAM_BANK0_ECC_SVBUS_ENABLE_SET | R/W1TS | 0h | Interrupt Enable Set Register for cpu0_a53_dual_u_tlb_spram_bank0_ecc_svbus_pend |
18 | CPU0_A53_DUAL_U_DDIRTY_SPRAM_ECC_SVBUS_ENABLE_SET | R/W1TS | 0h | Interrupt Enable Set Register for cpu0_a53_dual_u_ddirty_spram_ecc_svbus_pend |
17 | CPU0_A53_DUAL_U_DTAG_SPRAM_BANK3_ECC_SVBUS_ENABLE_SET | R/W1TS | 0h | Interrupt Enable Set Register for cpu0_a53_dual_u_dtag_spram_bank3_ecc_svbus_pend |
16 | CPU0_A53_DUAL_U_DTAG_SPRAM_BANK2_ECC_SVBUS_ENABLE_SET | R/W1TS | 0h | Interrupt Enable Set Register for cpu0_a53_dual_u_dtag_spram_bank2_ecc_svbus_pend |
15 | CPU0_A53_DUAL_U_DTAG_SPRAM_BANK1_ECC_SVBUS_ENABLE_SET | R/W1TS | 0h | Interrupt Enable Set Register for cpu0_a53_dual_u_dtag_spram_bank1_ecc_svbus_pend |
14 | CPU0_A53_DUAL_U_DTAG_SPRAM_BANK0_ECC_SVBUS_ENABLE_SET | R/W1TS | 0h | Interrupt Enable Set Register for cpu0_a53_dual_u_dtag_spram_bank0_ecc_svbus_pend |
13 | CPU0_A53_DUAL_U_DDATA_SPRAM_BANK7_ECC_SVBUS_ENABLE_SET | R/W1TS | 0h | Interrupt Enable Set Register for cpu0_a53_dual_u_ddata_spram_bank7_ecc_svbus_pend |
12 | CPU0_A53_DUAL_U_DDATA_SPRAM_BANK6_ECC_SVBUS_ENABLE_SET | R/W1TS | 0h | Interrupt Enable Set Register for cpu0_a53_dual_u_ddata_spram_bank6_ecc_svbus_pend |
11 | CPU0_A53_DUAL_U_DDATA_SPRAM_BANK5_ECC_SVBUS_ENABLE_SET | R/W1TS | 0h | Interrupt Enable Set Register for cpu0_a53_dual_u_ddata_spram_bank5_ecc_svbus_pend |
10 | CPU0_A53_DUAL_U_DDATA_SPRAM_BANK4_ECC_SVBUS_ENABLE_SET | R/W1TS | 0h | Interrupt Enable Set Register for cpu0_a53_dual_u_ddata_spram_bank4_ecc_svbus_pend |
9 | CPU0_A53_DUAL_U_DDATA_SPRAM_BANK3_ECC_SVBUS_ENABLE_SET | R/W1TS | 0h | Interrupt Enable Set Register for cpu0_a53_dual_u_ddata_spram_bank3_ecc_svbus_pend |
8 | CPU0_A53_DUAL_U_DDATA_SPRAM_BANK2_ECC_SVBUS_ENABLE_SET | R/W1TS | 0h | Interrupt Enable Set Register for cpu0_a53_dual_u_ddata_spram_bank2_ecc_svbus_pend |
7 | CPU0_A53_DUAL_U_DDATA_SPRAM_BANK1_ECC_SVBUS_ENABLE_SET | R/W1TS | 0h | Interrupt Enable Set Register for cpu0_a53_dual_u_ddata_spram_bank1_ecc_svbus_pend |
6 | CPU0_A53_DUAL_U_DDATA_SPRAM_BANK0_ECC_SVBUS_ENABLE_SET | R/W1TS | 0h | Interrupt Enable Set Register for cpu0_a53_dual_u_ddata_spram_bank0_ecc_svbus_pend |
5 | CPU0_A53_DUAL_U_ITAG_SPRAM_RAM1_ECC_SVBUS_ENABLE_SET | R/W1TS | 0h | Interrupt Enable Set Register for cpu0_a53_dual_u_itag_spram_ram1_ecc_svbus_pend |
4 | CPU0_A53_DUAL_U_ITAG_SPRAM_RAM0_ECC_SVBUS_ENABLE_SET | R/W1TS | 0h | Interrupt Enable Set Register for cpu0_a53_dual_u_itag_spram_ram0_ecc_svbus_pend |
3 | CPU0_A53_DUAL_U_IDATA_SPRAM_BANK1_HI_ECC_SVBUS_ENABLE_SET | R/W1TS | 0h | Interrupt Enable Set Register for cpu0_a53_dual_u_idata_spram_bank1_hi_ecc_svbus_pend |
2 | CPU0_A53_DUAL_U_IDATA_SPRAM_BANK1_LO_ECC_SVBUS_ENABLE_SET | R/W1TS | 0h | Interrupt Enable Set Register for cpu0_a53_dual_u_idata_spram_bank1_lo_ecc_svbus_pend |
1 | CPU0_A53_DUAL_U_IDATA_SPRAM_BANK0_HI_ECC_SVBUS_ENABLE_SET | R/W1TS | 0h | Interrupt Enable Set Register for cpu0_a53_dual_u_idata_spram_bank0_hi_ecc_svbus_pend |
0 | CPU0_A53_DUAL_U_IDATA_SPRAM_BANK0_LO_ECC_SVBUS_ENABLE_SET | R/W1TS | 0h | Interrupt Enable Set Register for cpu0_a53_dual_u_idata_spram_bank0_lo_ecc_svbus_pend |
Short Description: Interrupt Enable Clear Register 0
Long Description:
Return to Summary Table
Instance Name | Base Address |
---|---|
A53SS0 | 0071 74C0h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | CPU0_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY3_ECC_SVBUS_ENABLE_CLR | CPU0_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY2_ECC_SVBUS_ENABLE_CLR | CPU0_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY1_ECC_SVBUS_ENABLE_CLR | CPU0_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY0_ECC_SVBUS_ENABLE_CLR | CPU0_A53_DUAL_U_TLB_SPRAM_BANK3_ECC_SVBUS_ENABLE_CLR | CPU0_A53_DUAL_U_TLB_SPRAM_BANK2_ECC_SVBUS_ENABLE_CLR | CPU0_A53_DUAL_U_TLB_SPRAM_BANK1_ECC_SVBUS_ENABLE_CLR | CPU0_A53_DUAL_U_TLB_SPRAM_BANK0_ECC_SVBUS_ENABLE_CLR | CPU0_A53_DUAL_U_DDIRTY_SPRAM_ECC_SVBUS_ENABLE_CLR | CPU0_A53_DUAL_U_DTAG_SPRAM_BANK3_ECC_SVBUS_ENABLE_CLR | CPU0_A53_DUAL_U_DTAG_SPRAM_BANK2_ECC_SVBUS_ENABLE_CLR | ||||
NONE | R/W1TC | R/W1TC | R/W1TC | R/W1TC | R/W1TC | R/W1TC | R/W1TC | R/W1TC | R/W1TC | R/W1TC | R/W1TC | ||||
0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CPU0_A53_DUAL_U_DTAG_SPRAM_BANK1_ECC_SVBUS_ENABLE_CLR | CPU0_A53_DUAL_U_DTAG_SPRAM_BANK0_ECC_SVBUS_ENABLE_CLR | CPU0_A53_DUAL_U_DDATA_SPRAM_BANK7_ECC_SVBUS_ENABLE_CLR | CPU0_A53_DUAL_U_DDATA_SPRAM_BANK6_ECC_SVBUS_ENABLE_CLR | CPU0_A53_DUAL_U_DDATA_SPRAM_BANK5_ECC_SVBUS_ENABLE_CLR | CPU0_A53_DUAL_U_DDATA_SPRAM_BANK4_ECC_SVBUS_ENABLE_CLR | CPU0_A53_DUAL_U_DDATA_SPRAM_BANK3_ECC_SVBUS_ENABLE_CLR | CPU0_A53_DUAL_U_DDATA_SPRAM_BANK2_ECC_SVBUS_ENABLE_CLR | CPU0_A53_DUAL_U_DDATA_SPRAM_BANK1_ECC_SVBUS_ENABLE_CLR | CPU0_A53_DUAL_U_DDATA_SPRAM_BANK0_ECC_SVBUS_ENABLE_CLR | CPU0_A53_DUAL_U_ITAG_SPRAM_RAM1_ECC_SVBUS_ENABLE_CLR | CPU0_A53_DUAL_U_ITAG_SPRAM_RAM0_ECC_SVBUS_ENABLE_CLR | CPU0_A53_DUAL_U_IDATA_SPRAM_BANK1_HI_ECC_SVBUS_ENABLE_CLR | CPU0_A53_DUAL_U_IDATA_SPRAM_BANK1_LO_ECC_SVBUS_ENABLE_CLR | CPU0_A53_DUAL_U_IDATA_SPRAM_BANK0_HI_ECC_SVBUS_ENABLE_CLR | CPU0_A53_DUAL_U_IDATA_SPRAM_BANK0_LO_ECC_SVBUS_ENABLE_CLR |
R/W1TC | R/W1TC | R/W1TC | R/W1TC | R/W1TC | R/W1TC | R/W1TC | R/W1TC | R/W1TC | R/W1TC | R/W1TC | R/W1TC | R/W1TC | R/W1TC | R/W1TC | R/W1TC |
0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
RESERVED | NONE | Reserved | ||
26 | CPU0_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY3_ECC_SVBUS_ENABLE_CLR | R/W1TC | 0h | Interrupt Enable Clear Register for cpu0_a53_dual_u_l1d_tagram_spram_way3_ecc_svbus_pend |
25 | CPU0_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY2_ECC_SVBUS_ENABLE_CLR | R/W1TC | 0h | Interrupt Enable Clear Register for cpu0_a53_dual_u_l1d_tagram_spram_way2_ecc_svbus_pend |
24 | CPU0_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY1_ECC_SVBUS_ENABLE_CLR | R/W1TC | 0h | Interrupt Enable Clear Register for cpu0_a53_dual_u_l1d_tagram_spram_way1_ecc_svbus_pend |
23 | CPU0_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY0_ECC_SVBUS_ENABLE_CLR | R/W1TC | 0h | Interrupt Enable Clear Register for cpu0_a53_dual_u_l1d_tagram_spram_way0_ecc_svbus_pend |
22 | CPU0_A53_DUAL_U_TLB_SPRAM_BANK3_ECC_SVBUS_ENABLE_CLR | R/W1TC | 0h | Interrupt Enable Clear Register for cpu0_a53_dual_u_tlb_spram_bank3_ecc_svbus_pend |
21 | CPU0_A53_DUAL_U_TLB_SPRAM_BANK2_ECC_SVBUS_ENABLE_CLR | R/W1TC | 0h | Interrupt Enable Clear Register for cpu0_a53_dual_u_tlb_spram_bank2_ecc_svbus_pend |
20 | CPU0_A53_DUAL_U_TLB_SPRAM_BANK1_ECC_SVBUS_ENABLE_CLR | R/W1TC | 0h | Interrupt Enable Clear Register for cpu0_a53_dual_u_tlb_spram_bank1_ecc_svbus_pend |
19 | CPU0_A53_DUAL_U_TLB_SPRAM_BANK0_ECC_SVBUS_ENABLE_CLR | R/W1TC | 0h | Interrupt Enable Clear Register for cpu0_a53_dual_u_tlb_spram_bank0_ecc_svbus_pend |
18 | CPU0_A53_DUAL_U_DDIRTY_SPRAM_ECC_SVBUS_ENABLE_CLR | R/W1TC | 0h | Interrupt Enable Clear Register for cpu0_a53_dual_u_ddirty_spram_ecc_svbus_pend |
17 | CPU0_A53_DUAL_U_DTAG_SPRAM_BANK3_ECC_SVBUS_ENABLE_CLR | R/W1TC | 0h | Interrupt Enable Clear Register for cpu0_a53_dual_u_dtag_spram_bank3_ecc_svbus_pend |
16 | CPU0_A53_DUAL_U_DTAG_SPRAM_BANK2_ECC_SVBUS_ENABLE_CLR | R/W1TC | 0h | Interrupt Enable Clear Register for cpu0_a53_dual_u_dtag_spram_bank2_ecc_svbus_pend |
15 | CPU0_A53_DUAL_U_DTAG_SPRAM_BANK1_ECC_SVBUS_ENABLE_CLR | R/W1TC | 0h | Interrupt Enable Clear Register for cpu0_a53_dual_u_dtag_spram_bank1_ecc_svbus_pend |
14 | CPU0_A53_DUAL_U_DTAG_SPRAM_BANK0_ECC_SVBUS_ENABLE_CLR | R/W1TC | 0h | Interrupt Enable Clear Register for cpu0_a53_dual_u_dtag_spram_bank0_ecc_svbus_pend |
13 | CPU0_A53_DUAL_U_DDATA_SPRAM_BANK7_ECC_SVBUS_ENABLE_CLR | R/W1TC | 0h | Interrupt Enable Clear Register for cpu0_a53_dual_u_ddata_spram_bank7_ecc_svbus_pend |
12 | CPU0_A53_DUAL_U_DDATA_SPRAM_BANK6_ECC_SVBUS_ENABLE_CLR | R/W1TC | 0h | Interrupt Enable Clear Register for cpu0_a53_dual_u_ddata_spram_bank6_ecc_svbus_pend |
11 | CPU0_A53_DUAL_U_DDATA_SPRAM_BANK5_ECC_SVBUS_ENABLE_CLR | R/W1TC | 0h | Interrupt Enable Clear Register for cpu0_a53_dual_u_ddata_spram_bank5_ecc_svbus_pend |
10 | CPU0_A53_DUAL_U_DDATA_SPRAM_BANK4_ECC_SVBUS_ENABLE_CLR | R/W1TC | 0h | Interrupt Enable Clear Register for cpu0_a53_dual_u_ddata_spram_bank4_ecc_svbus_pend |
9 | CPU0_A53_DUAL_U_DDATA_SPRAM_BANK3_ECC_SVBUS_ENABLE_CLR | R/W1TC | 0h | Interrupt Enable Clear Register for cpu0_a53_dual_u_ddata_spram_bank3_ecc_svbus_pend |
8 | CPU0_A53_DUAL_U_DDATA_SPRAM_BANK2_ECC_SVBUS_ENABLE_CLR | R/W1TC | 0h | Interrupt Enable Clear Register for cpu0_a53_dual_u_ddata_spram_bank2_ecc_svbus_pend |
7 | CPU0_A53_DUAL_U_DDATA_SPRAM_BANK1_ECC_SVBUS_ENABLE_CLR | R/W1TC | 0h | Interrupt Enable Clear Register for cpu0_a53_dual_u_ddata_spram_bank1_ecc_svbus_pend |
6 | CPU0_A53_DUAL_U_DDATA_SPRAM_BANK0_ECC_SVBUS_ENABLE_CLR | R/W1TC | 0h | Interrupt Enable Clear Register for cpu0_a53_dual_u_ddata_spram_bank0_ecc_svbus_pend |
5 | CPU0_A53_DUAL_U_ITAG_SPRAM_RAM1_ECC_SVBUS_ENABLE_CLR | R/W1TC | 0h | Interrupt Enable Clear Register for cpu0_a53_dual_u_itag_spram_ram1_ecc_svbus_pend |
4 | CPU0_A53_DUAL_U_ITAG_SPRAM_RAM0_ECC_SVBUS_ENABLE_CLR | R/W1TC | 0h | Interrupt Enable Clear Register for cpu0_a53_dual_u_itag_spram_ram0_ecc_svbus_pend |
3 | CPU0_A53_DUAL_U_IDATA_SPRAM_BANK1_HI_ECC_SVBUS_ENABLE_CLR | R/W1TC | 0h | Interrupt Enable Clear Register for cpu0_a53_dual_u_idata_spram_bank1_hi_ecc_svbus_pend |
2 | CPU0_A53_DUAL_U_IDATA_SPRAM_BANK1_LO_ECC_SVBUS_ENABLE_CLR | R/W1TC | 0h | Interrupt Enable Clear Register for cpu0_a53_dual_u_idata_spram_bank1_lo_ecc_svbus_pend |
1 | CPU0_A53_DUAL_U_IDATA_SPRAM_BANK0_HI_ECC_SVBUS_ENABLE_CLR | R/W1TC | 0h | Interrupt Enable Clear Register for cpu0_a53_dual_u_idata_spram_bank0_hi_ecc_svbus_pend |
0 | CPU0_A53_DUAL_U_IDATA_SPRAM_BANK0_LO_ECC_SVBUS_ENABLE_CLR | R/W1TC | 0h | Interrupt Enable Clear Register for cpu0_a53_dual_u_idata_spram_bank0_lo_ecc_svbus_pend |
Short Description: EOI Register
Long Description:
Return to Summary Table
Instance Name | Base Address |
---|---|
A53SS0 | 0071 753Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
NONE | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | EOI_WR | ||||||||||||||
NONE | R/W1TS | ||||||||||||||
0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
RESERVED | NONE | Reserved | ||
0 | EOI_WR | R/W1TS | 0h | EOI Register |
Short Description: Interrupt Status Register 0
Long Description:
Return to Summary Table
Instance Name | Base Address |
---|---|
A53SS0 | 0071 7540h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | CPU0_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY3_ECC_SVBUS_PEND | CPU0_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY2_ECC_SVBUS_PEND | CPU0_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY1_ECC_SVBUS_PEND | CPU0_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY0_ECC_SVBUS_PEND | CPU0_A53_DUAL_U_TLB_SPRAM_BANK3_ECC_SVBUS_PEND | CPU0_A53_DUAL_U_TLB_SPRAM_BANK2_ECC_SVBUS_PEND | CPU0_A53_DUAL_U_TLB_SPRAM_BANK1_ECC_SVBUS_PEND | CPU0_A53_DUAL_U_TLB_SPRAM_BANK0_ECC_SVBUS_PEND | CPU0_A53_DUAL_U_DDIRTY_SPRAM_ECC_SVBUS_PEND | CPU0_A53_DUAL_U_DTAG_SPRAM_BANK3_ECC_SVBUS_PEND | CPU0_A53_DUAL_U_DTAG_SPRAM_BANK2_ECC_SVBUS_PEND | ||||
NONE | R/W1TS | R/W1TS | R/W1TS | R/W1TS | R/W1TS | R/W1TS | R/W1TS | R/W1TS | R/W1TS | R/W1TS | R/W1TS | ||||
0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CPU0_A53_DUAL_U_DTAG_SPRAM_BANK1_ECC_SVBUS_PEND | CPU0_A53_DUAL_U_DTAG_SPRAM_BANK0_ECC_SVBUS_PEND | CPU0_A53_DUAL_U_DDATA_SPRAM_BANK7_ECC_SVBUS_PEND | CPU0_A53_DUAL_U_DDATA_SPRAM_BANK6_ECC_SVBUS_PEND | CPU0_A53_DUAL_U_DDATA_SPRAM_BANK5_ECC_SVBUS_PEND | CPU0_A53_DUAL_U_DDATA_SPRAM_BANK4_ECC_SVBUS_PEND | CPU0_A53_DUAL_U_DDATA_SPRAM_BANK3_ECC_SVBUS_PEND | CPU0_A53_DUAL_U_DDATA_SPRAM_BANK2_ECC_SVBUS_PEND | CPU0_A53_DUAL_U_DDATA_SPRAM_BANK1_ECC_SVBUS_PEND | CPU0_A53_DUAL_U_DDATA_SPRAM_BANK0_ECC_SVBUS_PEND | CPU0_A53_DUAL_U_ITAG_SPRAM_RAM1_ECC_SVBUS_PEND | CPU0_A53_DUAL_U_ITAG_SPRAM_RAM0_ECC_SVBUS_PEND | CPU0_A53_DUAL_U_IDATA_SPRAM_BANK1_HI_ECC_SVBUS_PEND | CPU0_A53_DUAL_U_IDATA_SPRAM_BANK1_LO_ECC_SVBUS_PEND | CPU0_A53_DUAL_U_IDATA_SPRAM_BANK0_HI_ECC_SVBUS_PEND | CPU0_A53_DUAL_U_IDATA_SPRAM_BANK0_LO_ECC_SVBUS_PEND |
R/W1TS | R/W1TS | R/W1TS | R/W1TS | R/W1TS | R/W1TS | R/W1TS | R/W1TS | R/W1TS | R/W1TS | R/W1TS | R/W1TS | R/W1TS | R/W1TS | R/W1TS | R/W1TS |
0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
RESERVED | NONE | Reserved | ||
26 | CPU0_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY3_ECC_SVBUS_PEND | R/W1TS | 0h | Interrupt Pending Status for cpu0_a53_dual_u_l1d_tagram_spram_way3_ecc_svbus_pend |
25 | CPU0_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY2_ECC_SVBUS_PEND | R/W1TS | 0h | Interrupt Pending Status for cpu0_a53_dual_u_l1d_tagram_spram_way2_ecc_svbus_pend |
24 | CPU0_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY1_ECC_SVBUS_PEND | R/W1TS | 0h | Interrupt Pending Status for cpu0_a53_dual_u_l1d_tagram_spram_way1_ecc_svbus_pend |
23 | CPU0_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY0_ECC_SVBUS_PEND | R/W1TS | 0h | Interrupt Pending Status for cpu0_a53_dual_u_l1d_tagram_spram_way0_ecc_svbus_pend |
22 | CPU0_A53_DUAL_U_TLB_SPRAM_BANK3_ECC_SVBUS_PEND | R/W1TS | 0h | Interrupt Pending Status for cpu0_a53_dual_u_tlb_spram_bank3_ecc_svbus_pend |
21 | CPU0_A53_DUAL_U_TLB_SPRAM_BANK2_ECC_SVBUS_PEND | R/W1TS | 0h | Interrupt Pending Status for cpu0_a53_dual_u_tlb_spram_bank2_ecc_svbus_pend |
20 | CPU0_A53_DUAL_U_TLB_SPRAM_BANK1_ECC_SVBUS_PEND | R/W1TS | 0h | Interrupt Pending Status for cpu0_a53_dual_u_tlb_spram_bank1_ecc_svbus_pend |
19 | CPU0_A53_DUAL_U_TLB_SPRAM_BANK0_ECC_SVBUS_PEND | R/W1TS | 0h | Interrupt Pending Status for cpu0_a53_dual_u_tlb_spram_bank0_ecc_svbus_pend |
18 | CPU0_A53_DUAL_U_DDIRTY_SPRAM_ECC_SVBUS_PEND | R/W1TS | 0h | Interrupt Pending Status for cpu0_a53_dual_u_ddirty_spram_ecc_svbus_pend |
17 | CPU0_A53_DUAL_U_DTAG_SPRAM_BANK3_ECC_SVBUS_PEND | R/W1TS | 0h | Interrupt Pending Status for cpu0_a53_dual_u_dtag_spram_bank3_ecc_svbus_pend |
16 | CPU0_A53_DUAL_U_DTAG_SPRAM_BANK2_ECC_SVBUS_PEND | R/W1TS | 0h | Interrupt Pending Status for cpu0_a53_dual_u_dtag_spram_bank2_ecc_svbus_pend |
15 | CPU0_A53_DUAL_U_DTAG_SPRAM_BANK1_ECC_SVBUS_PEND | R/W1TS | 0h | Interrupt Pending Status for cpu0_a53_dual_u_dtag_spram_bank1_ecc_svbus_pend |
14 | CPU0_A53_DUAL_U_DTAG_SPRAM_BANK0_ECC_SVBUS_PEND | R/W1TS | 0h | Interrupt Pending Status for cpu0_a53_dual_u_dtag_spram_bank0_ecc_svbus_pend |
13 | CPU0_A53_DUAL_U_DDATA_SPRAM_BANK7_ECC_SVBUS_PEND | R/W1TS | 0h | Interrupt Pending Status for cpu0_a53_dual_u_ddata_spram_bank7_ecc_svbus_pend |
12 | CPU0_A53_DUAL_U_DDATA_SPRAM_BANK6_ECC_SVBUS_PEND | R/W1TS | 0h | Interrupt Pending Status for cpu0_a53_dual_u_ddata_spram_bank6_ecc_svbus_pend |
11 | CPU0_A53_DUAL_U_DDATA_SPRAM_BANK5_ECC_SVBUS_PEND | R/W1TS | 0h | Interrupt Pending Status for cpu0_a53_dual_u_ddata_spram_bank5_ecc_svbus_pend |
10 | CPU0_A53_DUAL_U_DDATA_SPRAM_BANK4_ECC_SVBUS_PEND | R/W1TS | 0h | Interrupt Pending Status for cpu0_a53_dual_u_ddata_spram_bank4_ecc_svbus_pend |
9 | CPU0_A53_DUAL_U_DDATA_SPRAM_BANK3_ECC_SVBUS_PEND | R/W1TS | 0h | Interrupt Pending Status for cpu0_a53_dual_u_ddata_spram_bank3_ecc_svbus_pend |
8 | CPU0_A53_DUAL_U_DDATA_SPRAM_BANK2_ECC_SVBUS_PEND | R/W1TS | 0h | Interrupt Pending Status for cpu0_a53_dual_u_ddata_spram_bank2_ecc_svbus_pend |
7 | CPU0_A53_DUAL_U_DDATA_SPRAM_BANK1_ECC_SVBUS_PEND | R/W1TS | 0h | Interrupt Pending Status for cpu0_a53_dual_u_ddata_spram_bank1_ecc_svbus_pend |
6 | CPU0_A53_DUAL_U_DDATA_SPRAM_BANK0_ECC_SVBUS_PEND | R/W1TS | 0h | Interrupt Pending Status for cpu0_a53_dual_u_ddata_spram_bank0_ecc_svbus_pend |
5 | CPU0_A53_DUAL_U_ITAG_SPRAM_RAM1_ECC_SVBUS_PEND | R/W1TS | 0h | Interrupt Pending Status for cpu0_a53_dual_u_itag_spram_ram1_ecc_svbus_pend |
4 | CPU0_A53_DUAL_U_ITAG_SPRAM_RAM0_ECC_SVBUS_PEND | R/W1TS | 0h | Interrupt Pending Status for cpu0_a53_dual_u_itag_spram_ram0_ecc_svbus_pend |
3 | CPU0_A53_DUAL_U_IDATA_SPRAM_BANK1_HI_ECC_SVBUS_PEND | R/W1TS | 0h | Interrupt Pending Status for cpu0_a53_dual_u_idata_spram_bank1_hi_ecc_svbus_pend |
2 | CPU0_A53_DUAL_U_IDATA_SPRAM_BANK1_LO_ECC_SVBUS_PEND | R/W1TS | 0h | Interrupt Pending Status for cpu0_a53_dual_u_idata_spram_bank1_lo_ecc_svbus_pend |
1 | CPU0_A53_DUAL_U_IDATA_SPRAM_BANK0_HI_ECC_SVBUS_PEND | R/W1TS | 0h | Interrupt Pending Status for cpu0_a53_dual_u_idata_spram_bank0_hi_ecc_svbus_pend |
0 | CPU0_A53_DUAL_U_IDATA_SPRAM_BANK0_LO_ECC_SVBUS_PEND | R/W1TS | 0h | Interrupt Pending Status for cpu0_a53_dual_u_idata_spram_bank0_lo_ecc_svbus_pend |
Short Description: Interrupt Enable Set Register 0
Long Description:
Return to Summary Table
Instance Name | Base Address |
---|---|
A53SS0 | 0071 7580h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | CPU0_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY3_ECC_SVBUS_ENABLE_SET | CPU0_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY2_ECC_SVBUS_ENABLE_SET | CPU0_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY1_ECC_SVBUS_ENABLE_SET | CPU0_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY0_ECC_SVBUS_ENABLE_SET | CPU0_A53_DUAL_U_TLB_SPRAM_BANK3_ECC_SVBUS_ENABLE_SET | CPU0_A53_DUAL_U_TLB_SPRAM_BANK2_ECC_SVBUS_ENABLE_SET | CPU0_A53_DUAL_U_TLB_SPRAM_BANK1_ECC_SVBUS_ENABLE_SET | CPU0_A53_DUAL_U_TLB_SPRAM_BANK0_ECC_SVBUS_ENABLE_SET | CPU0_A53_DUAL_U_DDIRTY_SPRAM_ECC_SVBUS_ENABLE_SET | CPU0_A53_DUAL_U_DTAG_SPRAM_BANK3_ECC_SVBUS_ENABLE_SET | CPU0_A53_DUAL_U_DTAG_SPRAM_BANK2_ECC_SVBUS_ENABLE_SET | ||||
NONE | R/W1TS | R/W1TS | R/W1TS | R/W1TS | R/W1TS | R/W1TS | R/W1TS | R/W1TS | R/W1TS | R/W1TS | R/W1TS | ||||
0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CPU0_A53_DUAL_U_DTAG_SPRAM_BANK1_ECC_SVBUS_ENABLE_SET | CPU0_A53_DUAL_U_DTAG_SPRAM_BANK0_ECC_SVBUS_ENABLE_SET | CPU0_A53_DUAL_U_DDATA_SPRAM_BANK7_ECC_SVBUS_ENABLE_SET | CPU0_A53_DUAL_U_DDATA_SPRAM_BANK6_ECC_SVBUS_ENABLE_SET | CPU0_A53_DUAL_U_DDATA_SPRAM_BANK5_ECC_SVBUS_ENABLE_SET | CPU0_A53_DUAL_U_DDATA_SPRAM_BANK4_ECC_SVBUS_ENABLE_SET | CPU0_A53_DUAL_U_DDATA_SPRAM_BANK3_ECC_SVBUS_ENABLE_SET | CPU0_A53_DUAL_U_DDATA_SPRAM_BANK2_ECC_SVBUS_ENABLE_SET | CPU0_A53_DUAL_U_DDATA_SPRAM_BANK1_ECC_SVBUS_ENABLE_SET | CPU0_A53_DUAL_U_DDATA_SPRAM_BANK0_ECC_SVBUS_ENABLE_SET | CPU0_A53_DUAL_U_ITAG_SPRAM_RAM1_ECC_SVBUS_ENABLE_SET | CPU0_A53_DUAL_U_ITAG_SPRAM_RAM0_ECC_SVBUS_ENABLE_SET | CPU0_A53_DUAL_U_IDATA_SPRAM_BANK1_HI_ECC_SVBUS_ENABLE_SET | CPU0_A53_DUAL_U_IDATA_SPRAM_BANK1_LO_ECC_SVBUS_ENABLE_SET | CPU0_A53_DUAL_U_IDATA_SPRAM_BANK0_HI_ECC_SVBUS_ENABLE_SET | CPU0_A53_DUAL_U_IDATA_SPRAM_BANK0_LO_ECC_SVBUS_ENABLE_SET |
R/W1TS | R/W1TS | R/W1TS | R/W1TS | R/W1TS | R/W1TS | R/W1TS | R/W1TS | R/W1TS | R/W1TS | R/W1TS | R/W1TS | R/W1TS | R/W1TS | R/W1TS | R/W1TS |
0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
RESERVED | NONE | Reserved | ||
26 | CPU0_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY3_ECC_SVBUS_ENABLE_SET | R/W1TS | 0h | Interrupt Enable Set Register for cpu0_a53_dual_u_l1d_tagram_spram_way3_ecc_svbus_pend |
25 | CPU0_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY2_ECC_SVBUS_ENABLE_SET | R/W1TS | 0h | Interrupt Enable Set Register for cpu0_a53_dual_u_l1d_tagram_spram_way2_ecc_svbus_pend |
24 | CPU0_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY1_ECC_SVBUS_ENABLE_SET | R/W1TS | 0h | Interrupt Enable Set Register for cpu0_a53_dual_u_l1d_tagram_spram_way1_ecc_svbus_pend |
23 | CPU0_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY0_ECC_SVBUS_ENABLE_SET | R/W1TS | 0h | Interrupt Enable Set Register for cpu0_a53_dual_u_l1d_tagram_spram_way0_ecc_svbus_pend |
22 | CPU0_A53_DUAL_U_TLB_SPRAM_BANK3_ECC_SVBUS_ENABLE_SET | R/W1TS | 0h | Interrupt Enable Set Register for cpu0_a53_dual_u_tlb_spram_bank3_ecc_svbus_pend |
21 | CPU0_A53_DUAL_U_TLB_SPRAM_BANK2_ECC_SVBUS_ENABLE_SET | R/W1TS | 0h | Interrupt Enable Set Register for cpu0_a53_dual_u_tlb_spram_bank2_ecc_svbus_pend |
20 | CPU0_A53_DUAL_U_TLB_SPRAM_BANK1_ECC_SVBUS_ENABLE_SET | R/W1TS | 0h | Interrupt Enable Set Register for cpu0_a53_dual_u_tlb_spram_bank1_ecc_svbus_pend |
19 | CPU0_A53_DUAL_U_TLB_SPRAM_BANK0_ECC_SVBUS_ENABLE_SET | R/W1TS | 0h | Interrupt Enable Set Register for cpu0_a53_dual_u_tlb_spram_bank0_ecc_svbus_pend |
18 | CPU0_A53_DUAL_U_DDIRTY_SPRAM_ECC_SVBUS_ENABLE_SET | R/W1TS | 0h | Interrupt Enable Set Register for cpu0_a53_dual_u_ddirty_spram_ecc_svbus_pend |
17 | CPU0_A53_DUAL_U_DTAG_SPRAM_BANK3_ECC_SVBUS_ENABLE_SET | R/W1TS | 0h | Interrupt Enable Set Register for cpu0_a53_dual_u_dtag_spram_bank3_ecc_svbus_pend |
16 | CPU0_A53_DUAL_U_DTAG_SPRAM_BANK2_ECC_SVBUS_ENABLE_SET | R/W1TS | 0h | Interrupt Enable Set Register for cpu0_a53_dual_u_dtag_spram_bank2_ecc_svbus_pend |
15 | CPU0_A53_DUAL_U_DTAG_SPRAM_BANK1_ECC_SVBUS_ENABLE_SET | R/W1TS | 0h | Interrupt Enable Set Register for cpu0_a53_dual_u_dtag_spram_bank1_ecc_svbus_pend |
14 | CPU0_A53_DUAL_U_DTAG_SPRAM_BANK0_ECC_SVBUS_ENABLE_SET | R/W1TS | 0h | Interrupt Enable Set Register for cpu0_a53_dual_u_dtag_spram_bank0_ecc_svbus_pend |
13 | CPU0_A53_DUAL_U_DDATA_SPRAM_BANK7_ECC_SVBUS_ENABLE_SET | R/W1TS | 0h | Interrupt Enable Set Register for cpu0_a53_dual_u_ddata_spram_bank7_ecc_svbus_pend |
12 | CPU0_A53_DUAL_U_DDATA_SPRAM_BANK6_ECC_SVBUS_ENABLE_SET | R/W1TS | 0h | Interrupt Enable Set Register for cpu0_a53_dual_u_ddata_spram_bank6_ecc_svbus_pend |
11 | CPU0_A53_DUAL_U_DDATA_SPRAM_BANK5_ECC_SVBUS_ENABLE_SET | R/W1TS | 0h | Interrupt Enable Set Register for cpu0_a53_dual_u_ddata_spram_bank5_ecc_svbus_pend |
10 | CPU0_A53_DUAL_U_DDATA_SPRAM_BANK4_ECC_SVBUS_ENABLE_SET | R/W1TS | 0h | Interrupt Enable Set Register for cpu0_a53_dual_u_ddata_spram_bank4_ecc_svbus_pend |
9 | CPU0_A53_DUAL_U_DDATA_SPRAM_BANK3_ECC_SVBUS_ENABLE_SET | R/W1TS | 0h | Interrupt Enable Set Register for cpu0_a53_dual_u_ddata_spram_bank3_ecc_svbus_pend |
8 | CPU0_A53_DUAL_U_DDATA_SPRAM_BANK2_ECC_SVBUS_ENABLE_SET | R/W1TS | 0h | Interrupt Enable Set Register for cpu0_a53_dual_u_ddata_spram_bank2_ecc_svbus_pend |
7 | CPU0_A53_DUAL_U_DDATA_SPRAM_BANK1_ECC_SVBUS_ENABLE_SET | R/W1TS | 0h | Interrupt Enable Set Register for cpu0_a53_dual_u_ddata_spram_bank1_ecc_svbus_pend |
6 | CPU0_A53_DUAL_U_DDATA_SPRAM_BANK0_ECC_SVBUS_ENABLE_SET | R/W1TS | 0h | Interrupt Enable Set Register for cpu0_a53_dual_u_ddata_spram_bank0_ecc_svbus_pend |
5 | CPU0_A53_DUAL_U_ITAG_SPRAM_RAM1_ECC_SVBUS_ENABLE_SET | R/W1TS | 0h | Interrupt Enable Set Register for cpu0_a53_dual_u_itag_spram_ram1_ecc_svbus_pend |
4 | CPU0_A53_DUAL_U_ITAG_SPRAM_RAM0_ECC_SVBUS_ENABLE_SET | R/W1TS | 0h | Interrupt Enable Set Register for cpu0_a53_dual_u_itag_spram_ram0_ecc_svbus_pend |
3 | CPU0_A53_DUAL_U_IDATA_SPRAM_BANK1_HI_ECC_SVBUS_ENABLE_SET | R/W1TS | 0h | Interrupt Enable Set Register for cpu0_a53_dual_u_idata_spram_bank1_hi_ecc_svbus_pend |
2 | CPU0_A53_DUAL_U_IDATA_SPRAM_BANK1_LO_ECC_SVBUS_ENABLE_SET | R/W1TS | 0h | Interrupt Enable Set Register for cpu0_a53_dual_u_idata_spram_bank1_lo_ecc_svbus_pend |
1 | CPU0_A53_DUAL_U_IDATA_SPRAM_BANK0_HI_ECC_SVBUS_ENABLE_SET | R/W1TS | 0h | Interrupt Enable Set Register for cpu0_a53_dual_u_idata_spram_bank0_hi_ecc_svbus_pend |
0 | CPU0_A53_DUAL_U_IDATA_SPRAM_BANK0_LO_ECC_SVBUS_ENABLE_SET | R/W1TS | 0h | Interrupt Enable Set Register for cpu0_a53_dual_u_idata_spram_bank0_lo_ecc_svbus_pend |
Short Description: Interrupt Enable Clear Register 0
Long Description:
Return to Summary Table
Instance Name | Base Address |
---|---|
A53SS0 | 0071 75C0h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | CPU0_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY3_ECC_SVBUS_ENABLE_CLR | CPU0_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY2_ECC_SVBUS_ENABLE_CLR | CPU0_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY1_ECC_SVBUS_ENABLE_CLR | CPU0_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY0_ECC_SVBUS_ENABLE_CLR | CPU0_A53_DUAL_U_TLB_SPRAM_BANK3_ECC_SVBUS_ENABLE_CLR | CPU0_A53_DUAL_U_TLB_SPRAM_BANK2_ECC_SVBUS_ENABLE_CLR | CPU0_A53_DUAL_U_TLB_SPRAM_BANK1_ECC_SVBUS_ENABLE_CLR | CPU0_A53_DUAL_U_TLB_SPRAM_BANK0_ECC_SVBUS_ENABLE_CLR | CPU0_A53_DUAL_U_DDIRTY_SPRAM_ECC_SVBUS_ENABLE_CLR | CPU0_A53_DUAL_U_DTAG_SPRAM_BANK3_ECC_SVBUS_ENABLE_CLR | CPU0_A53_DUAL_U_DTAG_SPRAM_BANK2_ECC_SVBUS_ENABLE_CLR | ||||
NONE | R/W1TC | R/W1TC | R/W1TC | R/W1TC | R/W1TC | R/W1TC | R/W1TC | R/W1TC | R/W1TC | R/W1TC | R/W1TC | ||||
0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CPU0_A53_DUAL_U_DTAG_SPRAM_BANK1_ECC_SVBUS_ENABLE_CLR | CPU0_A53_DUAL_U_DTAG_SPRAM_BANK0_ECC_SVBUS_ENABLE_CLR | CPU0_A53_DUAL_U_DDATA_SPRAM_BANK7_ECC_SVBUS_ENABLE_CLR | CPU0_A53_DUAL_U_DDATA_SPRAM_BANK6_ECC_SVBUS_ENABLE_CLR | CPU0_A53_DUAL_U_DDATA_SPRAM_BANK5_ECC_SVBUS_ENABLE_CLR | CPU0_A53_DUAL_U_DDATA_SPRAM_BANK4_ECC_SVBUS_ENABLE_CLR | CPU0_A53_DUAL_U_DDATA_SPRAM_BANK3_ECC_SVBUS_ENABLE_CLR | CPU0_A53_DUAL_U_DDATA_SPRAM_BANK2_ECC_SVBUS_ENABLE_CLR | CPU0_A53_DUAL_U_DDATA_SPRAM_BANK1_ECC_SVBUS_ENABLE_CLR | CPU0_A53_DUAL_U_DDATA_SPRAM_BANK0_ECC_SVBUS_ENABLE_CLR | CPU0_A53_DUAL_U_ITAG_SPRAM_RAM1_ECC_SVBUS_ENABLE_CLR | CPU0_A53_DUAL_U_ITAG_SPRAM_RAM0_ECC_SVBUS_ENABLE_CLR | CPU0_A53_DUAL_U_IDATA_SPRAM_BANK1_HI_ECC_SVBUS_ENABLE_CLR | CPU0_A53_DUAL_U_IDATA_SPRAM_BANK1_LO_ECC_SVBUS_ENABLE_CLR | CPU0_A53_DUAL_U_IDATA_SPRAM_BANK0_HI_ECC_SVBUS_ENABLE_CLR | CPU0_A53_DUAL_U_IDATA_SPRAM_BANK0_LO_ECC_SVBUS_ENABLE_CLR |
R/W1TC | R/W1TC | R/W1TC | R/W1TC | R/W1TC | R/W1TC | R/W1TC | R/W1TC | R/W1TC | R/W1TC | R/W1TC | R/W1TC | R/W1TC | R/W1TC | R/W1TC | R/W1TC |
0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
RESERVED | NONE | Reserved | ||
26 | CPU0_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY3_ECC_SVBUS_ENABLE_CLR | R/W1TC | 0h | Interrupt Enable Clear Register for cpu0_a53_dual_u_l1d_tagram_spram_way3_ecc_svbus_pend |
25 | CPU0_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY2_ECC_SVBUS_ENABLE_CLR | R/W1TC | 0h | Interrupt Enable Clear Register for cpu0_a53_dual_u_l1d_tagram_spram_way2_ecc_svbus_pend |
24 | CPU0_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY1_ECC_SVBUS_ENABLE_CLR | R/W1TC | 0h | Interrupt Enable Clear Register for cpu0_a53_dual_u_l1d_tagram_spram_way1_ecc_svbus_pend |
23 | CPU0_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY0_ECC_SVBUS_ENABLE_CLR | R/W1TC | 0h | Interrupt Enable Clear Register for cpu0_a53_dual_u_l1d_tagram_spram_way0_ecc_svbus_pend |
22 | CPU0_A53_DUAL_U_TLB_SPRAM_BANK3_ECC_SVBUS_ENABLE_CLR | R/W1TC | 0h | Interrupt Enable Clear Register for cpu0_a53_dual_u_tlb_spram_bank3_ecc_svbus_pend |
21 | CPU0_A53_DUAL_U_TLB_SPRAM_BANK2_ECC_SVBUS_ENABLE_CLR | R/W1TC | 0h | Interrupt Enable Clear Register for cpu0_a53_dual_u_tlb_spram_bank2_ecc_svbus_pend |
20 | CPU0_A53_DUAL_U_TLB_SPRAM_BANK1_ECC_SVBUS_ENABLE_CLR | R/W1TC | 0h | Interrupt Enable Clear Register for cpu0_a53_dual_u_tlb_spram_bank1_ecc_svbus_pend |
19 | CPU0_A53_DUAL_U_TLB_SPRAM_BANK0_ECC_SVBUS_ENABLE_CLR | R/W1TC | 0h | Interrupt Enable Clear Register for cpu0_a53_dual_u_tlb_spram_bank0_ecc_svbus_pend |
18 | CPU0_A53_DUAL_U_DDIRTY_SPRAM_ECC_SVBUS_ENABLE_CLR | R/W1TC | 0h | Interrupt Enable Clear Register for cpu0_a53_dual_u_ddirty_spram_ecc_svbus_pend |
17 | CPU0_A53_DUAL_U_DTAG_SPRAM_BANK3_ECC_SVBUS_ENABLE_CLR | R/W1TC | 0h | Interrupt Enable Clear Register for cpu0_a53_dual_u_dtag_spram_bank3_ecc_svbus_pend |
16 | CPU0_A53_DUAL_U_DTAG_SPRAM_BANK2_ECC_SVBUS_ENABLE_CLR | R/W1TC | 0h | Interrupt Enable Clear Register for cpu0_a53_dual_u_dtag_spram_bank2_ecc_svbus_pend |
15 | CPU0_A53_DUAL_U_DTAG_SPRAM_BANK1_ECC_SVBUS_ENABLE_CLR | R/W1TC | 0h | Interrupt Enable Clear Register for cpu0_a53_dual_u_dtag_spram_bank1_ecc_svbus_pend |
14 | CPU0_A53_DUAL_U_DTAG_SPRAM_BANK0_ECC_SVBUS_ENABLE_CLR | R/W1TC | 0h | Interrupt Enable Clear Register for cpu0_a53_dual_u_dtag_spram_bank0_ecc_svbus_pend |
13 | CPU0_A53_DUAL_U_DDATA_SPRAM_BANK7_ECC_SVBUS_ENABLE_CLR | R/W1TC | 0h | Interrupt Enable Clear Register for cpu0_a53_dual_u_ddata_spram_bank7_ecc_svbus_pend |
12 | CPU0_A53_DUAL_U_DDATA_SPRAM_BANK6_ECC_SVBUS_ENABLE_CLR | R/W1TC | 0h | Interrupt Enable Clear Register for cpu0_a53_dual_u_ddata_spram_bank6_ecc_svbus_pend |
11 | CPU0_A53_DUAL_U_DDATA_SPRAM_BANK5_ECC_SVBUS_ENABLE_CLR | R/W1TC | 0h | Interrupt Enable Clear Register for cpu0_a53_dual_u_ddata_spram_bank5_ecc_svbus_pend |
10 | CPU0_A53_DUAL_U_DDATA_SPRAM_BANK4_ECC_SVBUS_ENABLE_CLR | R/W1TC | 0h | Interrupt Enable Clear Register for cpu0_a53_dual_u_ddata_spram_bank4_ecc_svbus_pend |
9 | CPU0_A53_DUAL_U_DDATA_SPRAM_BANK3_ECC_SVBUS_ENABLE_CLR | R/W1TC | 0h | Interrupt Enable Clear Register for cpu0_a53_dual_u_ddata_spram_bank3_ecc_svbus_pend |
8 | CPU0_A53_DUAL_U_DDATA_SPRAM_BANK2_ECC_SVBUS_ENABLE_CLR | R/W1TC | 0h | Interrupt Enable Clear Register for cpu0_a53_dual_u_ddata_spram_bank2_ecc_svbus_pend |
7 | CPU0_A53_DUAL_U_DDATA_SPRAM_BANK1_ECC_SVBUS_ENABLE_CLR | R/W1TC | 0h | Interrupt Enable Clear Register for cpu0_a53_dual_u_ddata_spram_bank1_ecc_svbus_pend |
6 | CPU0_A53_DUAL_U_DDATA_SPRAM_BANK0_ECC_SVBUS_ENABLE_CLR | R/W1TC | 0h | Interrupt Enable Clear Register for cpu0_a53_dual_u_ddata_spram_bank0_ecc_svbus_pend |
5 | CPU0_A53_DUAL_U_ITAG_SPRAM_RAM1_ECC_SVBUS_ENABLE_CLR | R/W1TC | 0h | Interrupt Enable Clear Register for cpu0_a53_dual_u_itag_spram_ram1_ecc_svbus_pend |
4 | CPU0_A53_DUAL_U_ITAG_SPRAM_RAM0_ECC_SVBUS_ENABLE_CLR | R/W1TC | 0h | Interrupt Enable Clear Register for cpu0_a53_dual_u_itag_spram_ram0_ecc_svbus_pend |
3 | CPU0_A53_DUAL_U_IDATA_SPRAM_BANK1_HI_ECC_SVBUS_ENABLE_CLR | R/W1TC | 0h | Interrupt Enable Clear Register for cpu0_a53_dual_u_idata_spram_bank1_hi_ecc_svbus_pend |
2 | CPU0_A53_DUAL_U_IDATA_SPRAM_BANK1_LO_ECC_SVBUS_ENABLE_CLR | R/W1TC | 0h | Interrupt Enable Clear Register for cpu0_a53_dual_u_idata_spram_bank1_lo_ecc_svbus_pend |
1 | CPU0_A53_DUAL_U_IDATA_SPRAM_BANK0_HI_ECC_SVBUS_ENABLE_CLR | R/W1TC | 0h | Interrupt Enable Clear Register for cpu0_a53_dual_u_idata_spram_bank0_hi_ecc_svbus_pend |
0 | CPU0_A53_DUAL_U_IDATA_SPRAM_BANK0_LO_ECC_SVBUS_ENABLE_CLR | R/W1TC | 0h | Interrupt Enable Clear Register for cpu0_a53_dual_u_idata_spram_bank0_lo_ecc_svbus_pend |
Short Description: AGGR interrupt enable set Register
Long Description:
Return to Summary Table
Instance Name | Base Address |
---|---|
A53SS0 | 0071 7600h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
NONE | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | TIMEOUT | PARITY | |||||||||||||
NONE | R/W1TS | R/W1TS | |||||||||||||
0 | 0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
RESERVED | NONE | Reserved | ||
1 | TIMEOUT | R/W1TS | 0h | interrupt enable set for svbus timeout errors |
0 | PARITY | R/W1TS | 0h | interrupt enable set for parity errors |
Short Description: AGGR interrupt enable clear Register
Long Description:
Return to Summary Table
Instance Name | Base Address |
---|---|
A53SS0 | 0071 7604h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
NONE | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | TIMEOUT | PARITY | |||||||||||||
NONE | R/W1TC | R/W1TC | |||||||||||||
0 | 0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
RESERVED | NONE | Reserved | ||
1 | TIMEOUT | R/W1TC | 0h | interrupt enable clear for svbus timeout errors |
0 | PARITY | R/W1TC | 0h | interrupt enable clear for parity errors |
Short Description: AGGR interrupt status set Register
Long Description:
Return to Summary Table
Instance Name | Base Address |
---|---|
A53SS0 | 0071 7608h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
NONE | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | TIMEOUT | PARITY | |||||||||||||
NONE | R/WI | R/WI | |||||||||||||
0 | 0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
RESERVED | NONE | Reserved | ||
3 - 2 | TIMEOUT | R/WI | 0h | interrupt status set for svbus timeout errors |
1 - 0 | PARITY | R/WI | 0h | interrupt status set for parity errors |
Short Description: AGGR interrupt status clear Register
Long Description:
Return to Summary Table
Instance Name | Base Address |
---|---|
A53SS0 | 0071 760Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
NONE | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | TIMEOUT | PARITY | |||||||||||||
NONE | R/WD | R/WD | |||||||||||||
0 | 0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
RESERVED | NONE | Reserved | ||
3 - 2 | TIMEOUT | R/WD | 0h | interrupt status clear for svbus timeout errors |
1 - 0 | PARITY | R/WD | 0h | interrupt status clear for parity errors |
Short Description: Aggregator Revision Register
Long Description:
Return to Summary Table
Instance Name | Base Address |
---|---|
A53SS0 | 0071 7800h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
SCHEME | BU | MODULE_ID | |||||||||||||
R | R | R | |||||||||||||
1 | 10 | 11010100000 | |||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
REVRTL | REVMAJ | CUSTOM | REVMIN | ||||||||||||
R | R | R | R | ||||||||||||
101 | 10 | 0 | 1 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 - 30 | SCHEME | R | 1h | Scheme |
29 - 28 | BU | R | 2h | bu |
27 - 16 | MODULE_ID | R | 6A0h | Module ID |
15 - 11 | REVRTL | R | 5h | RTL version |
10 - 8 | REVMAJ | R | 2h | Major version |
7 - 6 | CUSTOM | R | 0h | Custom version |
5 - 0 | REVMIN | R | 1h | Minor version |
Short Description: ECC Vector Register
Long Description:
Return to Summary Table
Instance Name | Base Address |
---|---|
A53SS0 | 0071 7808h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | RD_SVBUS_DONE | RD_SVBUS_ADDRESS | |||||||||||||
NONE | R/W1TC | R/W | |||||||||||||
0 | 0 | ||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RD_SVBUS | RESERVED | ECC_VECTOR | |||||||||||||
R/W1TS | NONE | R/W | |||||||||||||
0 | 0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
RESERVED | NONE | Reserved | ||
24 | RD_SVBUS_DONE | R/W1TC | 0h | Status to indicate if read on serial VBUS is complete, write of any value will clear this bit. |
23 - 16 | RD_SVBUS_ADDRESS | R/W | 0h | Read address |
15 | RD_SVBUS | R/W1TS | 0h | Write 1 to trigger a read on the serial VBUS |
RESERVED | NONE | Reserved | ||
10 - 0 | ECC_VECTOR | R/W | 0h | Value written to select the corresponding ECC RAM for control or status |
Short Description: Misc Status
Long Description:
Return to Summary Table
Instance Name | Base Address |
---|---|
A53SS0 | 0071 780Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
NONE | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | NUM_RAMS | ||||||||||||||
NONE | R | ||||||||||||||
11011 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
RESERVED | NONE | Reserved | ||
10 - 0 | NUM_RAMS | R | 1Bh | Indicates the number of RAMS serviced by the ECC aggregator |
Short Description: Reserved Area for Serial VBUS Registers
Long Description:
Return to Summary Table
Instance Name | Base Address |
---|---|
A53SS0 | 0071 7810h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
DATA | |||||||||||||||
R/W | |||||||||||||||
0 | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DATA | |||||||||||||||
R/W | |||||||||||||||
0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 - 0 | DATA | R/W | 0h | Serial VBUS register data |
Short Description: EOI Register
Long Description:
Return to Summary Table
Instance Name | Base Address |
---|---|
A53SS0 | 0071 783Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
NONE | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | EOI_WR | ||||||||||||||
NONE | R/W1TS | ||||||||||||||
0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
RESERVED | NONE | Reserved | ||
0 | EOI_WR | R/W1TS | 0h | EOI Register |
Short Description: Interrupt Status Register 0
Long Description:
Return to Summary Table
Instance Name | Base Address |
---|---|
A53SS0 | 0071 7840h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | CPU1_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY3_ECC_SVBUS_PEND | CPU1_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY2_ECC_SVBUS_PEND | CPU1_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY1_ECC_SVBUS_PEND | CPU1_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY0_ECC_SVBUS_PEND | CPU1_A53_DUAL_U_TLB_SPRAM_BANK3_ECC_SVBUS_PEND | CPU1_A53_DUAL_U_TLB_SPRAM_BANK2_ECC_SVBUS_PEND | CPU1_A53_DUAL_U_TLB_SPRAM_BANK1_ECC_SVBUS_PEND | CPU1_A53_DUAL_U_TLB_SPRAM_BANK0_ECC_SVBUS_PEND | CPU1_A53_DUAL_U_DDIRTY_SPRAM_ECC_SVBUS_PEND | CPU1_A53_DUAL_U_DTAG_SPRAM_BANK3_ECC_SVBUS_PEND | CPU1_A53_DUAL_U_DTAG_SPRAM_BANK2_ECC_SVBUS_PEND | ||||
NONE | R/W1TS | R/W1TS | R/W1TS | R/W1TS | R/W1TS | R/W1TS | R/W1TS | R/W1TS | R/W1TS | R/W1TS | R/W1TS | ||||
0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CPU1_A53_DUAL_U_DTAG_SPRAM_BANK1_ECC_SVBUS_PEND | CPU1_A53_DUAL_U_DTAG_SPRAM_BANK0_ECC_SVBUS_PEND | CPU1_A53_DUAL_U_DDATA_SPRAM_BANK7_ECC_SVBUS_PEND | CPU1_A53_DUAL_U_DDATA_SPRAM_BANK6_ECC_SVBUS_PEND | CPU1_A53_DUAL_U_DDATA_SPRAM_BANK5_ECC_SVBUS_PEND | CPU1_A53_DUAL_U_DDATA_SPRAM_BANK4_ECC_SVBUS_PEND | CPU1_A53_DUAL_U_DDATA_SPRAM_BANK3_ECC_SVBUS_PEND | CPU1_A53_DUAL_U_DDATA_SPRAM_BANK2_ECC_SVBUS_PEND | CPU1_A53_DUAL_U_DDATA_SPRAM_BANK1_ECC_SVBUS_PEND | CPU1_A53_DUAL_U_DDATA_SPRAM_BANK0_ECC_SVBUS_PEND | CPU1_A53_DUAL_U_ITAG_SPRAM_RAM1_ECC_SVBUS_PEND | CPU1_A53_DUAL_U_ITAG_SPRAM_RAM0_ECC_SVBUS_PEND | CPU1_A53_DUAL_U_IDATA_SPRAM_BANK1_HI_ECC_SVBUS_PEND | CPU1_A53_DUAL_U_IDATA_SPRAM_BANK1_LO_ECC_SVBUS_PEND | CPU1_A53_DUAL_U_IDATA_SPRAM_BANK0_HI_ECC_SVBUS_PEND | CPU1_A53_DUAL_U_IDATA_SPRAM_BANK0_LO_ECC_SVBUS_PEND |
R/W1TS | R/W1TS | R/W1TS | R/W1TS | R/W1TS | R/W1TS | R/W1TS | R/W1TS | R/W1TS | R/W1TS | R/W1TS | R/W1TS | R/W1TS | R/W1TS | R/W1TS | R/W1TS |
0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
RESERVED | NONE | Reserved | ||
26 | CPU1_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY3_ECC_SVBUS_PEND | R/W1TS | 0h | Interrupt Pending Status for cpu1_a53_dual_u_l1d_tagram_spram_way3_ecc_svbus_pend |
25 | CPU1_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY2_ECC_SVBUS_PEND | R/W1TS | 0h | Interrupt Pending Status for cpu1_a53_dual_u_l1d_tagram_spram_way2_ecc_svbus_pend |
24 | CPU1_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY1_ECC_SVBUS_PEND | R/W1TS | 0h | Interrupt Pending Status for cpu1_a53_dual_u_l1d_tagram_spram_way1_ecc_svbus_pend |
23 | CPU1_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY0_ECC_SVBUS_PEND | R/W1TS | 0h | Interrupt Pending Status for cpu1_a53_dual_u_l1d_tagram_spram_way0_ecc_svbus_pend |
22 | CPU1_A53_DUAL_U_TLB_SPRAM_BANK3_ECC_SVBUS_PEND | R/W1TS | 0h | Interrupt Pending Status for cpu1_a53_dual_u_tlb_spram_bank3_ecc_svbus_pend |
21 | CPU1_A53_DUAL_U_TLB_SPRAM_BANK2_ECC_SVBUS_PEND | R/W1TS | 0h | Interrupt Pending Status for cpu1_a53_dual_u_tlb_spram_bank2_ecc_svbus_pend |
20 | CPU1_A53_DUAL_U_TLB_SPRAM_BANK1_ECC_SVBUS_PEND | R/W1TS | 0h | Interrupt Pending Status for cpu1_a53_dual_u_tlb_spram_bank1_ecc_svbus_pend |
19 | CPU1_A53_DUAL_U_TLB_SPRAM_BANK0_ECC_SVBUS_PEND | R/W1TS | 0h | Interrupt Pending Status for cpu1_a53_dual_u_tlb_spram_bank0_ecc_svbus_pend |
18 | CPU1_A53_DUAL_U_DDIRTY_SPRAM_ECC_SVBUS_PEND | R/W1TS | 0h | Interrupt Pending Status for cpu1_a53_dual_u_ddirty_spram_ecc_svbus_pend |
17 | CPU1_A53_DUAL_U_DTAG_SPRAM_BANK3_ECC_SVBUS_PEND | R/W1TS | 0h | Interrupt Pending Status for cpu1_a53_dual_u_dtag_spram_bank3_ecc_svbus_pend |
16 | CPU1_A53_DUAL_U_DTAG_SPRAM_BANK2_ECC_SVBUS_PEND | R/W1TS | 0h | Interrupt Pending Status for cpu1_a53_dual_u_dtag_spram_bank2_ecc_svbus_pend |
15 | CPU1_A53_DUAL_U_DTAG_SPRAM_BANK1_ECC_SVBUS_PEND | R/W1TS | 0h | Interrupt Pending Status for cpu1_a53_dual_u_dtag_spram_bank1_ecc_svbus_pend |
14 | CPU1_A53_DUAL_U_DTAG_SPRAM_BANK0_ECC_SVBUS_PEND | R/W1TS | 0h | Interrupt Pending Status for cpu1_a53_dual_u_dtag_spram_bank0_ecc_svbus_pend |
13 | CPU1_A53_DUAL_U_DDATA_SPRAM_BANK7_ECC_SVBUS_PEND | R/W1TS | 0h | Interrupt Pending Status for cpu1_a53_dual_u_ddata_spram_bank7_ecc_svbus_pend |
12 | CPU1_A53_DUAL_U_DDATA_SPRAM_BANK6_ECC_SVBUS_PEND | R/W1TS | 0h | Interrupt Pending Status for cpu1_a53_dual_u_ddata_spram_bank6_ecc_svbus_pend |
11 | CPU1_A53_DUAL_U_DDATA_SPRAM_BANK5_ECC_SVBUS_PEND | R/W1TS | 0h | Interrupt Pending Status for cpu1_a53_dual_u_ddata_spram_bank5_ecc_svbus_pend |
10 | CPU1_A53_DUAL_U_DDATA_SPRAM_BANK4_ECC_SVBUS_PEND | R/W1TS | 0h | Interrupt Pending Status for cpu1_a53_dual_u_ddata_spram_bank4_ecc_svbus_pend |
9 | CPU1_A53_DUAL_U_DDATA_SPRAM_BANK3_ECC_SVBUS_PEND | R/W1TS | 0h | Interrupt Pending Status for cpu1_a53_dual_u_ddata_spram_bank3_ecc_svbus_pend |
8 | CPU1_A53_DUAL_U_DDATA_SPRAM_BANK2_ECC_SVBUS_PEND | R/W1TS | 0h | Interrupt Pending Status for cpu1_a53_dual_u_ddata_spram_bank2_ecc_svbus_pend |
7 | CPU1_A53_DUAL_U_DDATA_SPRAM_BANK1_ECC_SVBUS_PEND | R/W1TS | 0h | Interrupt Pending Status for cpu1_a53_dual_u_ddata_spram_bank1_ecc_svbus_pend |
6 | CPU1_A53_DUAL_U_DDATA_SPRAM_BANK0_ECC_SVBUS_PEND | R/W1TS | 0h | Interrupt Pending Status for cpu1_a53_dual_u_ddata_spram_bank0_ecc_svbus_pend |
5 | CPU1_A53_DUAL_U_ITAG_SPRAM_RAM1_ECC_SVBUS_PEND | R/W1TS | 0h | Interrupt Pending Status for cpu1_a53_dual_u_itag_spram_ram1_ecc_svbus_pend |
4 | CPU1_A53_DUAL_U_ITAG_SPRAM_RAM0_ECC_SVBUS_PEND | R/W1TS | 0h | Interrupt Pending Status for cpu1_a53_dual_u_itag_spram_ram0_ecc_svbus_pend |
3 | CPU1_A53_DUAL_U_IDATA_SPRAM_BANK1_HI_ECC_SVBUS_PEND | R/W1TS | 0h | Interrupt Pending Status for cpu1_a53_dual_u_idata_spram_bank1_hi_ecc_svbus_pend |
2 | CPU1_A53_DUAL_U_IDATA_SPRAM_BANK1_LO_ECC_SVBUS_PEND | R/W1TS | 0h | Interrupt Pending Status for cpu1_a53_dual_u_idata_spram_bank1_lo_ecc_svbus_pend |
1 | CPU1_A53_DUAL_U_IDATA_SPRAM_BANK0_HI_ECC_SVBUS_PEND | R/W1TS | 0h | Interrupt Pending Status for cpu1_a53_dual_u_idata_spram_bank0_hi_ecc_svbus_pend |
0 | CPU1_A53_DUAL_U_IDATA_SPRAM_BANK0_LO_ECC_SVBUS_PEND | R/W1TS | 0h | Interrupt Pending Status for cpu1_a53_dual_u_idata_spram_bank0_lo_ecc_svbus_pend |
Short Description: Interrupt Enable Set Register 0
Long Description:
Return to Summary Table
Instance Name | Base Address |
---|---|
A53SS0 | 0071 7880h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | CPU1_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY3_ECC_SVBUS_ENABLE_SET | CPU1_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY2_ECC_SVBUS_ENABLE_SET | CPU1_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY1_ECC_SVBUS_ENABLE_SET | CPU1_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY0_ECC_SVBUS_ENABLE_SET | CPU1_A53_DUAL_U_TLB_SPRAM_BANK3_ECC_SVBUS_ENABLE_SET | CPU1_A53_DUAL_U_TLB_SPRAM_BANK2_ECC_SVBUS_ENABLE_SET | CPU1_A53_DUAL_U_TLB_SPRAM_BANK1_ECC_SVBUS_ENABLE_SET | CPU1_A53_DUAL_U_TLB_SPRAM_BANK0_ECC_SVBUS_ENABLE_SET | CPU1_A53_DUAL_U_DDIRTY_SPRAM_ECC_SVBUS_ENABLE_SET | CPU1_A53_DUAL_U_DTAG_SPRAM_BANK3_ECC_SVBUS_ENABLE_SET | CPU1_A53_DUAL_U_DTAG_SPRAM_BANK2_ECC_SVBUS_ENABLE_SET | ||||
NONE | R/W1TS | R/W1TS | R/W1TS | R/W1TS | R/W1TS | R/W1TS | R/W1TS | R/W1TS | R/W1TS | R/W1TS | R/W1TS | ||||
0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CPU1_A53_DUAL_U_DTAG_SPRAM_BANK1_ECC_SVBUS_ENABLE_SET | CPU1_A53_DUAL_U_DTAG_SPRAM_BANK0_ECC_SVBUS_ENABLE_SET | CPU1_A53_DUAL_U_DDATA_SPRAM_BANK7_ECC_SVBUS_ENABLE_SET | CPU1_A53_DUAL_U_DDATA_SPRAM_BANK6_ECC_SVBUS_ENABLE_SET | CPU1_A53_DUAL_U_DDATA_SPRAM_BANK5_ECC_SVBUS_ENABLE_SET | CPU1_A53_DUAL_U_DDATA_SPRAM_BANK4_ECC_SVBUS_ENABLE_SET | CPU1_A53_DUAL_U_DDATA_SPRAM_BANK3_ECC_SVBUS_ENABLE_SET | CPU1_A53_DUAL_U_DDATA_SPRAM_BANK2_ECC_SVBUS_ENABLE_SET | CPU1_A53_DUAL_U_DDATA_SPRAM_BANK1_ECC_SVBUS_ENABLE_SET | CPU1_A53_DUAL_U_DDATA_SPRAM_BANK0_ECC_SVBUS_ENABLE_SET | CPU1_A53_DUAL_U_ITAG_SPRAM_RAM1_ECC_SVBUS_ENABLE_SET | CPU1_A53_DUAL_U_ITAG_SPRAM_RAM0_ECC_SVBUS_ENABLE_SET | CPU1_A53_DUAL_U_IDATA_SPRAM_BANK1_HI_ECC_SVBUS_ENABLE_SET | CPU1_A53_DUAL_U_IDATA_SPRAM_BANK1_LO_ECC_SVBUS_ENABLE_SET | CPU1_A53_DUAL_U_IDATA_SPRAM_BANK0_HI_ECC_SVBUS_ENABLE_SET | CPU1_A53_DUAL_U_IDATA_SPRAM_BANK0_LO_ECC_SVBUS_ENABLE_SET |
R/W1TS | R/W1TS | R/W1TS | R/W1TS | R/W1TS | R/W1TS | R/W1TS | R/W1TS | R/W1TS | R/W1TS | R/W1TS | R/W1TS | R/W1TS | R/W1TS | R/W1TS | R/W1TS |
0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
RESERVED | NONE | Reserved | ||
26 | CPU1_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY3_ECC_SVBUS_ENABLE_SET | R/W1TS | 0h | Interrupt Enable Set Register for cpu1_a53_dual_u_l1d_tagram_spram_way3_ecc_svbus_pend |
25 | CPU1_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY2_ECC_SVBUS_ENABLE_SET | R/W1TS | 0h | Interrupt Enable Set Register for cpu1_a53_dual_u_l1d_tagram_spram_way2_ecc_svbus_pend |
24 | CPU1_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY1_ECC_SVBUS_ENABLE_SET | R/W1TS | 0h | Interrupt Enable Set Register for cpu1_a53_dual_u_l1d_tagram_spram_way1_ecc_svbus_pend |
23 | CPU1_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY0_ECC_SVBUS_ENABLE_SET | R/W1TS | 0h | Interrupt Enable Set Register for cpu1_a53_dual_u_l1d_tagram_spram_way0_ecc_svbus_pend |
22 | CPU1_A53_DUAL_U_TLB_SPRAM_BANK3_ECC_SVBUS_ENABLE_SET | R/W1TS | 0h | Interrupt Enable Set Register for cpu1_a53_dual_u_tlb_spram_bank3_ecc_svbus_pend |
21 | CPU1_A53_DUAL_U_TLB_SPRAM_BANK2_ECC_SVBUS_ENABLE_SET | R/W1TS | 0h | Interrupt Enable Set Register for cpu1_a53_dual_u_tlb_spram_bank2_ecc_svbus_pend |
20 | CPU1_A53_DUAL_U_TLB_SPRAM_BANK1_ECC_SVBUS_ENABLE_SET | R/W1TS | 0h | Interrupt Enable Set Register for cpu1_a53_dual_u_tlb_spram_bank1_ecc_svbus_pend |
19 | CPU1_A53_DUAL_U_TLB_SPRAM_BANK0_ECC_SVBUS_ENABLE_SET | R/W1TS | 0h | Interrupt Enable Set Register for cpu1_a53_dual_u_tlb_spram_bank0_ecc_svbus_pend |
18 | CPU1_A53_DUAL_U_DDIRTY_SPRAM_ECC_SVBUS_ENABLE_SET | R/W1TS | 0h | Interrupt Enable Set Register for cpu1_a53_dual_u_ddirty_spram_ecc_svbus_pend |
17 | CPU1_A53_DUAL_U_DTAG_SPRAM_BANK3_ECC_SVBUS_ENABLE_SET | R/W1TS | 0h | Interrupt Enable Set Register for cpu1_a53_dual_u_dtag_spram_bank3_ecc_svbus_pend |
16 | CPU1_A53_DUAL_U_DTAG_SPRAM_BANK2_ECC_SVBUS_ENABLE_SET | R/W1TS | 0h | Interrupt Enable Set Register for cpu1_a53_dual_u_dtag_spram_bank2_ecc_svbus_pend |
15 | CPU1_A53_DUAL_U_DTAG_SPRAM_BANK1_ECC_SVBUS_ENABLE_SET | R/W1TS | 0h | Interrupt Enable Set Register for cpu1_a53_dual_u_dtag_spram_bank1_ecc_svbus_pend |
14 | CPU1_A53_DUAL_U_DTAG_SPRAM_BANK0_ECC_SVBUS_ENABLE_SET | R/W1TS | 0h | Interrupt Enable Set Register for cpu1_a53_dual_u_dtag_spram_bank0_ecc_svbus_pend |
13 | CPU1_A53_DUAL_U_DDATA_SPRAM_BANK7_ECC_SVBUS_ENABLE_SET | R/W1TS | 0h | Interrupt Enable Set Register for cpu1_a53_dual_u_ddata_spram_bank7_ecc_svbus_pend |
12 | CPU1_A53_DUAL_U_DDATA_SPRAM_BANK6_ECC_SVBUS_ENABLE_SET | R/W1TS | 0h | Interrupt Enable Set Register for cpu1_a53_dual_u_ddata_spram_bank6_ecc_svbus_pend |
11 | CPU1_A53_DUAL_U_DDATA_SPRAM_BANK5_ECC_SVBUS_ENABLE_SET | R/W1TS | 0h | Interrupt Enable Set Register for cpu1_a53_dual_u_ddata_spram_bank5_ecc_svbus_pend |
10 | CPU1_A53_DUAL_U_DDATA_SPRAM_BANK4_ECC_SVBUS_ENABLE_SET | R/W1TS | 0h | Interrupt Enable Set Register for cpu1_a53_dual_u_ddata_spram_bank4_ecc_svbus_pend |
9 | CPU1_A53_DUAL_U_DDATA_SPRAM_BANK3_ECC_SVBUS_ENABLE_SET | R/W1TS | 0h | Interrupt Enable Set Register for cpu1_a53_dual_u_ddata_spram_bank3_ecc_svbus_pend |
8 | CPU1_A53_DUAL_U_DDATA_SPRAM_BANK2_ECC_SVBUS_ENABLE_SET | R/W1TS | 0h | Interrupt Enable Set Register for cpu1_a53_dual_u_ddata_spram_bank2_ecc_svbus_pend |
7 | CPU1_A53_DUAL_U_DDATA_SPRAM_BANK1_ECC_SVBUS_ENABLE_SET | R/W1TS | 0h | Interrupt Enable Set Register for cpu1_a53_dual_u_ddata_spram_bank1_ecc_svbus_pend |
6 | CPU1_A53_DUAL_U_DDATA_SPRAM_BANK0_ECC_SVBUS_ENABLE_SET | R/W1TS | 0h | Interrupt Enable Set Register for cpu1_a53_dual_u_ddata_spram_bank0_ecc_svbus_pend |
5 | CPU1_A53_DUAL_U_ITAG_SPRAM_RAM1_ECC_SVBUS_ENABLE_SET | R/W1TS | 0h | Interrupt Enable Set Register for cpu1_a53_dual_u_itag_spram_ram1_ecc_svbus_pend |
4 | CPU1_A53_DUAL_U_ITAG_SPRAM_RAM0_ECC_SVBUS_ENABLE_SET | R/W1TS | 0h | Interrupt Enable Set Register for cpu1_a53_dual_u_itag_spram_ram0_ecc_svbus_pend |
3 | CPU1_A53_DUAL_U_IDATA_SPRAM_BANK1_HI_ECC_SVBUS_ENABLE_SET | R/W1TS | 0h | Interrupt Enable Set Register for cpu1_a53_dual_u_idata_spram_bank1_hi_ecc_svbus_pend |
2 | CPU1_A53_DUAL_U_IDATA_SPRAM_BANK1_LO_ECC_SVBUS_ENABLE_SET | R/W1TS | 0h | Interrupt Enable Set Register for cpu1_a53_dual_u_idata_spram_bank1_lo_ecc_svbus_pend |
1 | CPU1_A53_DUAL_U_IDATA_SPRAM_BANK0_HI_ECC_SVBUS_ENABLE_SET | R/W1TS | 0h | Interrupt Enable Set Register for cpu1_a53_dual_u_idata_spram_bank0_hi_ecc_svbus_pend |
0 | CPU1_A53_DUAL_U_IDATA_SPRAM_BANK0_LO_ECC_SVBUS_ENABLE_SET | R/W1TS | 0h | Interrupt Enable Set Register for cpu1_a53_dual_u_idata_spram_bank0_lo_ecc_svbus_pend |
Short Description: Interrupt Enable Clear Register 0
Long Description:
Return to Summary Table
Instance Name | Base Address |
---|---|
A53SS0 | 0071 78C0h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | CPU1_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY3_ECC_SVBUS_ENABLE_CLR | CPU1_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY2_ECC_SVBUS_ENABLE_CLR | CPU1_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY1_ECC_SVBUS_ENABLE_CLR | CPU1_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY0_ECC_SVBUS_ENABLE_CLR | CPU1_A53_DUAL_U_TLB_SPRAM_BANK3_ECC_SVBUS_ENABLE_CLR | CPU1_A53_DUAL_U_TLB_SPRAM_BANK2_ECC_SVBUS_ENABLE_CLR | CPU1_A53_DUAL_U_TLB_SPRAM_BANK1_ECC_SVBUS_ENABLE_CLR | CPU1_A53_DUAL_U_TLB_SPRAM_BANK0_ECC_SVBUS_ENABLE_CLR | CPU1_A53_DUAL_U_DDIRTY_SPRAM_ECC_SVBUS_ENABLE_CLR | CPU1_A53_DUAL_U_DTAG_SPRAM_BANK3_ECC_SVBUS_ENABLE_CLR | CPU1_A53_DUAL_U_DTAG_SPRAM_BANK2_ECC_SVBUS_ENABLE_CLR | ||||
NONE | R/W1TC | R/W1TC | R/W1TC | R/W1TC | R/W1TC | R/W1TC | R/W1TC | R/W1TC | R/W1TC | R/W1TC | R/W1TC | ||||
0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CPU1_A53_DUAL_U_DTAG_SPRAM_BANK1_ECC_SVBUS_ENABLE_CLR | CPU1_A53_DUAL_U_DTAG_SPRAM_BANK0_ECC_SVBUS_ENABLE_CLR | CPU1_A53_DUAL_U_DDATA_SPRAM_BANK7_ECC_SVBUS_ENABLE_CLR | CPU1_A53_DUAL_U_DDATA_SPRAM_BANK6_ECC_SVBUS_ENABLE_CLR | CPU1_A53_DUAL_U_DDATA_SPRAM_BANK5_ECC_SVBUS_ENABLE_CLR | CPU1_A53_DUAL_U_DDATA_SPRAM_BANK4_ECC_SVBUS_ENABLE_CLR | CPU1_A53_DUAL_U_DDATA_SPRAM_BANK3_ECC_SVBUS_ENABLE_CLR | CPU1_A53_DUAL_U_DDATA_SPRAM_BANK2_ECC_SVBUS_ENABLE_CLR | CPU1_A53_DUAL_U_DDATA_SPRAM_BANK1_ECC_SVBUS_ENABLE_CLR | CPU1_A53_DUAL_U_DDATA_SPRAM_BANK0_ECC_SVBUS_ENABLE_CLR | CPU1_A53_DUAL_U_ITAG_SPRAM_RAM1_ECC_SVBUS_ENABLE_CLR | CPU1_A53_DUAL_U_ITAG_SPRAM_RAM0_ECC_SVBUS_ENABLE_CLR | CPU1_A53_DUAL_U_IDATA_SPRAM_BANK1_HI_ECC_SVBUS_ENABLE_CLR | CPU1_A53_DUAL_U_IDATA_SPRAM_BANK1_LO_ECC_SVBUS_ENABLE_CLR | CPU1_A53_DUAL_U_IDATA_SPRAM_BANK0_HI_ECC_SVBUS_ENABLE_CLR | CPU1_A53_DUAL_U_IDATA_SPRAM_BANK0_LO_ECC_SVBUS_ENABLE_CLR |
R/W1TC | R/W1TC | R/W1TC | R/W1TC | R/W1TC | R/W1TC | R/W1TC | R/W1TC | R/W1TC | R/W1TC | R/W1TC | R/W1TC | R/W1TC | R/W1TC | R/W1TC | R/W1TC |
0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
RESERVED | NONE | Reserved | ||
26 | CPU1_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY3_ECC_SVBUS_ENABLE_CLR | R/W1TC | 0h | Interrupt Enable Clear Register for cpu1_a53_dual_u_l1d_tagram_spram_way3_ecc_svbus_pend |
25 | CPU1_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY2_ECC_SVBUS_ENABLE_CLR | R/W1TC | 0h | Interrupt Enable Clear Register for cpu1_a53_dual_u_l1d_tagram_spram_way2_ecc_svbus_pend |
24 | CPU1_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY1_ECC_SVBUS_ENABLE_CLR | R/W1TC | 0h | Interrupt Enable Clear Register for cpu1_a53_dual_u_l1d_tagram_spram_way1_ecc_svbus_pend |
23 | CPU1_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY0_ECC_SVBUS_ENABLE_CLR | R/W1TC | 0h | Interrupt Enable Clear Register for cpu1_a53_dual_u_l1d_tagram_spram_way0_ecc_svbus_pend |
22 | CPU1_A53_DUAL_U_TLB_SPRAM_BANK3_ECC_SVBUS_ENABLE_CLR | R/W1TC | 0h | Interrupt Enable Clear Register for cpu1_a53_dual_u_tlb_spram_bank3_ecc_svbus_pend |
21 | CPU1_A53_DUAL_U_TLB_SPRAM_BANK2_ECC_SVBUS_ENABLE_CLR | R/W1TC | 0h | Interrupt Enable Clear Register for cpu1_a53_dual_u_tlb_spram_bank2_ecc_svbus_pend |
20 | CPU1_A53_DUAL_U_TLB_SPRAM_BANK1_ECC_SVBUS_ENABLE_CLR | R/W1TC | 0h | Interrupt Enable Clear Register for cpu1_a53_dual_u_tlb_spram_bank1_ecc_svbus_pend |
19 | CPU1_A53_DUAL_U_TLB_SPRAM_BANK0_ECC_SVBUS_ENABLE_CLR | R/W1TC | 0h | Interrupt Enable Clear Register for cpu1_a53_dual_u_tlb_spram_bank0_ecc_svbus_pend |
18 | CPU1_A53_DUAL_U_DDIRTY_SPRAM_ECC_SVBUS_ENABLE_CLR | R/W1TC | 0h | Interrupt Enable Clear Register for cpu1_a53_dual_u_ddirty_spram_ecc_svbus_pend |
17 | CPU1_A53_DUAL_U_DTAG_SPRAM_BANK3_ECC_SVBUS_ENABLE_CLR | R/W1TC | 0h | Interrupt Enable Clear Register for cpu1_a53_dual_u_dtag_spram_bank3_ecc_svbus_pend |
16 | CPU1_A53_DUAL_U_DTAG_SPRAM_BANK2_ECC_SVBUS_ENABLE_CLR | R/W1TC | 0h | Interrupt Enable Clear Register for cpu1_a53_dual_u_dtag_spram_bank2_ecc_svbus_pend |
15 | CPU1_A53_DUAL_U_DTAG_SPRAM_BANK1_ECC_SVBUS_ENABLE_CLR | R/W1TC | 0h | Interrupt Enable Clear Register for cpu1_a53_dual_u_dtag_spram_bank1_ecc_svbus_pend |
14 | CPU1_A53_DUAL_U_DTAG_SPRAM_BANK0_ECC_SVBUS_ENABLE_CLR | R/W1TC | 0h | Interrupt Enable Clear Register for cpu1_a53_dual_u_dtag_spram_bank0_ecc_svbus_pend |
13 | CPU1_A53_DUAL_U_DDATA_SPRAM_BANK7_ECC_SVBUS_ENABLE_CLR | R/W1TC | 0h | Interrupt Enable Clear Register for cpu1_a53_dual_u_ddata_spram_bank7_ecc_svbus_pend |
12 | CPU1_A53_DUAL_U_DDATA_SPRAM_BANK6_ECC_SVBUS_ENABLE_CLR | R/W1TC | 0h | Interrupt Enable Clear Register for cpu1_a53_dual_u_ddata_spram_bank6_ecc_svbus_pend |
11 | CPU1_A53_DUAL_U_DDATA_SPRAM_BANK5_ECC_SVBUS_ENABLE_CLR | R/W1TC | 0h | Interrupt Enable Clear Register for cpu1_a53_dual_u_ddata_spram_bank5_ecc_svbus_pend |
10 | CPU1_A53_DUAL_U_DDATA_SPRAM_BANK4_ECC_SVBUS_ENABLE_CLR | R/W1TC | 0h | Interrupt Enable Clear Register for cpu1_a53_dual_u_ddata_spram_bank4_ecc_svbus_pend |
9 | CPU1_A53_DUAL_U_DDATA_SPRAM_BANK3_ECC_SVBUS_ENABLE_CLR | R/W1TC | 0h | Interrupt Enable Clear Register for cpu1_a53_dual_u_ddata_spram_bank3_ecc_svbus_pend |
8 | CPU1_A53_DUAL_U_DDATA_SPRAM_BANK2_ECC_SVBUS_ENABLE_CLR | R/W1TC | 0h | Interrupt Enable Clear Register for cpu1_a53_dual_u_ddata_spram_bank2_ecc_svbus_pend |
7 | CPU1_A53_DUAL_U_DDATA_SPRAM_BANK1_ECC_SVBUS_ENABLE_CLR | R/W1TC | 0h | Interrupt Enable Clear Register for cpu1_a53_dual_u_ddata_spram_bank1_ecc_svbus_pend |
6 | CPU1_A53_DUAL_U_DDATA_SPRAM_BANK0_ECC_SVBUS_ENABLE_CLR | R/W1TC | 0h | Interrupt Enable Clear Register for cpu1_a53_dual_u_ddata_spram_bank0_ecc_svbus_pend |
5 | CPU1_A53_DUAL_U_ITAG_SPRAM_RAM1_ECC_SVBUS_ENABLE_CLR | R/W1TC | 0h | Interrupt Enable Clear Register for cpu1_a53_dual_u_itag_spram_ram1_ecc_svbus_pend |
4 | CPU1_A53_DUAL_U_ITAG_SPRAM_RAM0_ECC_SVBUS_ENABLE_CLR | R/W1TC | 0h | Interrupt Enable Clear Register for cpu1_a53_dual_u_itag_spram_ram0_ecc_svbus_pend |
3 | CPU1_A53_DUAL_U_IDATA_SPRAM_BANK1_HI_ECC_SVBUS_ENABLE_CLR | R/W1TC | 0h | Interrupt Enable Clear Register for cpu1_a53_dual_u_idata_spram_bank1_hi_ecc_svbus_pend |
2 | CPU1_A53_DUAL_U_IDATA_SPRAM_BANK1_LO_ECC_SVBUS_ENABLE_CLR | R/W1TC | 0h | Interrupt Enable Clear Register for cpu1_a53_dual_u_idata_spram_bank1_lo_ecc_svbus_pend |
1 | CPU1_A53_DUAL_U_IDATA_SPRAM_BANK0_HI_ECC_SVBUS_ENABLE_CLR | R/W1TC | 0h | Interrupt Enable Clear Register for cpu1_a53_dual_u_idata_spram_bank0_hi_ecc_svbus_pend |
0 | CPU1_A53_DUAL_U_IDATA_SPRAM_BANK0_LO_ECC_SVBUS_ENABLE_CLR | R/W1TC | 0h | Interrupt Enable Clear Register for cpu1_a53_dual_u_idata_spram_bank0_lo_ecc_svbus_pend |
Short Description: EOI Register
Long Description:
Return to Summary Table
Instance Name | Base Address |
---|---|
A53SS0 | 0071 793Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
NONE | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | EOI_WR | ||||||||||||||
NONE | R/W1TS | ||||||||||||||
0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
RESERVED | NONE | Reserved | ||
0 | EOI_WR | R/W1TS | 0h | EOI Register |
Short Description: Interrupt Status Register 0
Long Description:
Return to Summary Table
Instance Name | Base Address |
---|---|
A53SS0 | 0071 7940h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | CPU1_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY3_ECC_SVBUS_PEND | CPU1_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY2_ECC_SVBUS_PEND | CPU1_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY1_ECC_SVBUS_PEND | CPU1_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY0_ECC_SVBUS_PEND | CPU1_A53_DUAL_U_TLB_SPRAM_BANK3_ECC_SVBUS_PEND | CPU1_A53_DUAL_U_TLB_SPRAM_BANK2_ECC_SVBUS_PEND | CPU1_A53_DUAL_U_TLB_SPRAM_BANK1_ECC_SVBUS_PEND | CPU1_A53_DUAL_U_TLB_SPRAM_BANK0_ECC_SVBUS_PEND | CPU1_A53_DUAL_U_DDIRTY_SPRAM_ECC_SVBUS_PEND | CPU1_A53_DUAL_U_DTAG_SPRAM_BANK3_ECC_SVBUS_PEND | CPU1_A53_DUAL_U_DTAG_SPRAM_BANK2_ECC_SVBUS_PEND | ||||
NONE | R/W1TS | R/W1TS | R/W1TS | R/W1TS | R/W1TS | R/W1TS | R/W1TS | R/W1TS | R/W1TS | R/W1TS | R/W1TS | ||||
0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CPU1_A53_DUAL_U_DTAG_SPRAM_BANK1_ECC_SVBUS_PEND | CPU1_A53_DUAL_U_DTAG_SPRAM_BANK0_ECC_SVBUS_PEND | CPU1_A53_DUAL_U_DDATA_SPRAM_BANK7_ECC_SVBUS_PEND | CPU1_A53_DUAL_U_DDATA_SPRAM_BANK6_ECC_SVBUS_PEND | CPU1_A53_DUAL_U_DDATA_SPRAM_BANK5_ECC_SVBUS_PEND | CPU1_A53_DUAL_U_DDATA_SPRAM_BANK4_ECC_SVBUS_PEND | CPU1_A53_DUAL_U_DDATA_SPRAM_BANK3_ECC_SVBUS_PEND | CPU1_A53_DUAL_U_DDATA_SPRAM_BANK2_ECC_SVBUS_PEND | CPU1_A53_DUAL_U_DDATA_SPRAM_BANK1_ECC_SVBUS_PEND | CPU1_A53_DUAL_U_DDATA_SPRAM_BANK0_ECC_SVBUS_PEND | CPU1_A53_DUAL_U_ITAG_SPRAM_RAM1_ECC_SVBUS_PEND | CPU1_A53_DUAL_U_ITAG_SPRAM_RAM0_ECC_SVBUS_PEND | CPU1_A53_DUAL_U_IDATA_SPRAM_BANK1_HI_ECC_SVBUS_PEND | CPU1_A53_DUAL_U_IDATA_SPRAM_BANK1_LO_ECC_SVBUS_PEND | CPU1_A53_DUAL_U_IDATA_SPRAM_BANK0_HI_ECC_SVBUS_PEND | CPU1_A53_DUAL_U_IDATA_SPRAM_BANK0_LO_ECC_SVBUS_PEND |
R/W1TS | R/W1TS | R/W1TS | R/W1TS | R/W1TS | R/W1TS | R/W1TS | R/W1TS | R/W1TS | R/W1TS | R/W1TS | R/W1TS | R/W1TS | R/W1TS | R/W1TS | R/W1TS |
0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
RESERVED | NONE | Reserved | ||
26 | CPU1_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY3_ECC_SVBUS_PEND | R/W1TS | 0h | Interrupt Pending Status for cpu1_a53_dual_u_l1d_tagram_spram_way3_ecc_svbus_pend |
25 | CPU1_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY2_ECC_SVBUS_PEND | R/W1TS | 0h | Interrupt Pending Status for cpu1_a53_dual_u_l1d_tagram_spram_way2_ecc_svbus_pend |
24 | CPU1_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY1_ECC_SVBUS_PEND | R/W1TS | 0h | Interrupt Pending Status for cpu1_a53_dual_u_l1d_tagram_spram_way1_ecc_svbus_pend |
23 | CPU1_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY0_ECC_SVBUS_PEND | R/W1TS | 0h | Interrupt Pending Status for cpu1_a53_dual_u_l1d_tagram_spram_way0_ecc_svbus_pend |
22 | CPU1_A53_DUAL_U_TLB_SPRAM_BANK3_ECC_SVBUS_PEND | R/W1TS | 0h | Interrupt Pending Status for cpu1_a53_dual_u_tlb_spram_bank3_ecc_svbus_pend |
21 | CPU1_A53_DUAL_U_TLB_SPRAM_BANK2_ECC_SVBUS_PEND | R/W1TS | 0h | Interrupt Pending Status for cpu1_a53_dual_u_tlb_spram_bank2_ecc_svbus_pend |
20 | CPU1_A53_DUAL_U_TLB_SPRAM_BANK1_ECC_SVBUS_PEND | R/W1TS | 0h | Interrupt Pending Status for cpu1_a53_dual_u_tlb_spram_bank1_ecc_svbus_pend |
19 | CPU1_A53_DUAL_U_TLB_SPRAM_BANK0_ECC_SVBUS_PEND | R/W1TS | 0h | Interrupt Pending Status for cpu1_a53_dual_u_tlb_spram_bank0_ecc_svbus_pend |
18 | CPU1_A53_DUAL_U_DDIRTY_SPRAM_ECC_SVBUS_PEND | R/W1TS | 0h | Interrupt Pending Status for cpu1_a53_dual_u_ddirty_spram_ecc_svbus_pend |
17 | CPU1_A53_DUAL_U_DTAG_SPRAM_BANK3_ECC_SVBUS_PEND | R/W1TS | 0h | Interrupt Pending Status for cpu1_a53_dual_u_dtag_spram_bank3_ecc_svbus_pend |
16 | CPU1_A53_DUAL_U_DTAG_SPRAM_BANK2_ECC_SVBUS_PEND | R/W1TS | 0h | Interrupt Pending Status for cpu1_a53_dual_u_dtag_spram_bank2_ecc_svbus_pend |
15 | CPU1_A53_DUAL_U_DTAG_SPRAM_BANK1_ECC_SVBUS_PEND | R/W1TS | 0h | Interrupt Pending Status for cpu1_a53_dual_u_dtag_spram_bank1_ecc_svbus_pend |
14 | CPU1_A53_DUAL_U_DTAG_SPRAM_BANK0_ECC_SVBUS_PEND | R/W1TS | 0h | Interrupt Pending Status for cpu1_a53_dual_u_dtag_spram_bank0_ecc_svbus_pend |
13 | CPU1_A53_DUAL_U_DDATA_SPRAM_BANK7_ECC_SVBUS_PEND | R/W1TS | 0h | Interrupt Pending Status for cpu1_a53_dual_u_ddata_spram_bank7_ecc_svbus_pend |
12 | CPU1_A53_DUAL_U_DDATA_SPRAM_BANK6_ECC_SVBUS_PEND | R/W1TS | 0h | Interrupt Pending Status for cpu1_a53_dual_u_ddata_spram_bank6_ecc_svbus_pend |
11 | CPU1_A53_DUAL_U_DDATA_SPRAM_BANK5_ECC_SVBUS_PEND | R/W1TS | 0h | Interrupt Pending Status for cpu1_a53_dual_u_ddata_spram_bank5_ecc_svbus_pend |
10 | CPU1_A53_DUAL_U_DDATA_SPRAM_BANK4_ECC_SVBUS_PEND | R/W1TS | 0h | Interrupt Pending Status for cpu1_a53_dual_u_ddata_spram_bank4_ecc_svbus_pend |
9 | CPU1_A53_DUAL_U_DDATA_SPRAM_BANK3_ECC_SVBUS_PEND | R/W1TS | 0h | Interrupt Pending Status for cpu1_a53_dual_u_ddata_spram_bank3_ecc_svbus_pend |
8 | CPU1_A53_DUAL_U_DDATA_SPRAM_BANK2_ECC_SVBUS_PEND | R/W1TS | 0h | Interrupt Pending Status for cpu1_a53_dual_u_ddata_spram_bank2_ecc_svbus_pend |
7 | CPU1_A53_DUAL_U_DDATA_SPRAM_BANK1_ECC_SVBUS_PEND | R/W1TS | 0h | Interrupt Pending Status for cpu1_a53_dual_u_ddata_spram_bank1_ecc_svbus_pend |
6 | CPU1_A53_DUAL_U_DDATA_SPRAM_BANK0_ECC_SVBUS_PEND | R/W1TS | 0h | Interrupt Pending Status for cpu1_a53_dual_u_ddata_spram_bank0_ecc_svbus_pend |
5 | CPU1_A53_DUAL_U_ITAG_SPRAM_RAM1_ECC_SVBUS_PEND | R/W1TS | 0h | Interrupt Pending Status for cpu1_a53_dual_u_itag_spram_ram1_ecc_svbus_pend |
4 | CPU1_A53_DUAL_U_ITAG_SPRAM_RAM0_ECC_SVBUS_PEND | R/W1TS | 0h | Interrupt Pending Status for cpu1_a53_dual_u_itag_spram_ram0_ecc_svbus_pend |
3 | CPU1_A53_DUAL_U_IDATA_SPRAM_BANK1_HI_ECC_SVBUS_PEND | R/W1TS | 0h | Interrupt Pending Status for cpu1_a53_dual_u_idata_spram_bank1_hi_ecc_svbus_pend |
2 | CPU1_A53_DUAL_U_IDATA_SPRAM_BANK1_LO_ECC_SVBUS_PEND | R/W1TS | 0h | Interrupt Pending Status for cpu1_a53_dual_u_idata_spram_bank1_lo_ecc_svbus_pend |
1 | CPU1_A53_DUAL_U_IDATA_SPRAM_BANK0_HI_ECC_SVBUS_PEND | R/W1TS | 0h | Interrupt Pending Status for cpu1_a53_dual_u_idata_spram_bank0_hi_ecc_svbus_pend |
0 | CPU1_A53_DUAL_U_IDATA_SPRAM_BANK0_LO_ECC_SVBUS_PEND | R/W1TS | 0h | Interrupt Pending Status for cpu1_a53_dual_u_idata_spram_bank0_lo_ecc_svbus_pend |
Short Description: Interrupt Enable Set Register 0
Long Description:
Return to Summary Table
Instance Name | Base Address |
---|---|
A53SS0 | 0071 7980h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | CPU1_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY3_ECC_SVBUS_ENABLE_SET | CPU1_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY2_ECC_SVBUS_ENABLE_SET | CPU1_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY1_ECC_SVBUS_ENABLE_SET | CPU1_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY0_ECC_SVBUS_ENABLE_SET | CPU1_A53_DUAL_U_TLB_SPRAM_BANK3_ECC_SVBUS_ENABLE_SET | CPU1_A53_DUAL_U_TLB_SPRAM_BANK2_ECC_SVBUS_ENABLE_SET | CPU1_A53_DUAL_U_TLB_SPRAM_BANK1_ECC_SVBUS_ENABLE_SET | CPU1_A53_DUAL_U_TLB_SPRAM_BANK0_ECC_SVBUS_ENABLE_SET | CPU1_A53_DUAL_U_DDIRTY_SPRAM_ECC_SVBUS_ENABLE_SET | CPU1_A53_DUAL_U_DTAG_SPRAM_BANK3_ECC_SVBUS_ENABLE_SET | CPU1_A53_DUAL_U_DTAG_SPRAM_BANK2_ECC_SVBUS_ENABLE_SET | ||||
NONE | R/W1TS | R/W1TS | R/W1TS | R/W1TS | R/W1TS | R/W1TS | R/W1TS | R/W1TS | R/W1TS | R/W1TS | R/W1TS | ||||
0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CPU1_A53_DUAL_U_DTAG_SPRAM_BANK1_ECC_SVBUS_ENABLE_SET | CPU1_A53_DUAL_U_DTAG_SPRAM_BANK0_ECC_SVBUS_ENABLE_SET | CPU1_A53_DUAL_U_DDATA_SPRAM_BANK7_ECC_SVBUS_ENABLE_SET | CPU1_A53_DUAL_U_DDATA_SPRAM_BANK6_ECC_SVBUS_ENABLE_SET | CPU1_A53_DUAL_U_DDATA_SPRAM_BANK5_ECC_SVBUS_ENABLE_SET | CPU1_A53_DUAL_U_DDATA_SPRAM_BANK4_ECC_SVBUS_ENABLE_SET | CPU1_A53_DUAL_U_DDATA_SPRAM_BANK3_ECC_SVBUS_ENABLE_SET | CPU1_A53_DUAL_U_DDATA_SPRAM_BANK2_ECC_SVBUS_ENABLE_SET | CPU1_A53_DUAL_U_DDATA_SPRAM_BANK1_ECC_SVBUS_ENABLE_SET | CPU1_A53_DUAL_U_DDATA_SPRAM_BANK0_ECC_SVBUS_ENABLE_SET | CPU1_A53_DUAL_U_ITAG_SPRAM_RAM1_ECC_SVBUS_ENABLE_SET | CPU1_A53_DUAL_U_ITAG_SPRAM_RAM0_ECC_SVBUS_ENABLE_SET | CPU1_A53_DUAL_U_IDATA_SPRAM_BANK1_HI_ECC_SVBUS_ENABLE_SET | CPU1_A53_DUAL_U_IDATA_SPRAM_BANK1_LO_ECC_SVBUS_ENABLE_SET | CPU1_A53_DUAL_U_IDATA_SPRAM_BANK0_HI_ECC_SVBUS_ENABLE_SET | CPU1_A53_DUAL_U_IDATA_SPRAM_BANK0_LO_ECC_SVBUS_ENABLE_SET |
R/W1TS | R/W1TS | R/W1TS | R/W1TS | R/W1TS | R/W1TS | R/W1TS | R/W1TS | R/W1TS | R/W1TS | R/W1TS | R/W1TS | R/W1TS | R/W1TS | R/W1TS | R/W1TS |
0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
RESERVED | NONE | Reserved | ||
26 | CPU1_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY3_ECC_SVBUS_ENABLE_SET | R/W1TS | 0h | Interrupt Enable Set Register for cpu1_a53_dual_u_l1d_tagram_spram_way3_ecc_svbus_pend |
25 | CPU1_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY2_ECC_SVBUS_ENABLE_SET | R/W1TS | 0h | Interrupt Enable Set Register for cpu1_a53_dual_u_l1d_tagram_spram_way2_ecc_svbus_pend |
24 | CPU1_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY1_ECC_SVBUS_ENABLE_SET | R/W1TS | 0h | Interrupt Enable Set Register for cpu1_a53_dual_u_l1d_tagram_spram_way1_ecc_svbus_pend |
23 | CPU1_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY0_ECC_SVBUS_ENABLE_SET | R/W1TS | 0h | Interrupt Enable Set Register for cpu1_a53_dual_u_l1d_tagram_spram_way0_ecc_svbus_pend |
22 | CPU1_A53_DUAL_U_TLB_SPRAM_BANK3_ECC_SVBUS_ENABLE_SET | R/W1TS | 0h | Interrupt Enable Set Register for cpu1_a53_dual_u_tlb_spram_bank3_ecc_svbus_pend |
21 | CPU1_A53_DUAL_U_TLB_SPRAM_BANK2_ECC_SVBUS_ENABLE_SET | R/W1TS | 0h | Interrupt Enable Set Register for cpu1_a53_dual_u_tlb_spram_bank2_ecc_svbus_pend |
20 | CPU1_A53_DUAL_U_TLB_SPRAM_BANK1_ECC_SVBUS_ENABLE_SET | R/W1TS | 0h | Interrupt Enable Set Register for cpu1_a53_dual_u_tlb_spram_bank1_ecc_svbus_pend |
19 | CPU1_A53_DUAL_U_TLB_SPRAM_BANK0_ECC_SVBUS_ENABLE_SET | R/W1TS | 0h | Interrupt Enable Set Register for cpu1_a53_dual_u_tlb_spram_bank0_ecc_svbus_pend |
18 | CPU1_A53_DUAL_U_DDIRTY_SPRAM_ECC_SVBUS_ENABLE_SET | R/W1TS | 0h | Interrupt Enable Set Register for cpu1_a53_dual_u_ddirty_spram_ecc_svbus_pend |
17 | CPU1_A53_DUAL_U_DTAG_SPRAM_BANK3_ECC_SVBUS_ENABLE_SET | R/W1TS | 0h | Interrupt Enable Set Register for cpu1_a53_dual_u_dtag_spram_bank3_ecc_svbus_pend |
16 | CPU1_A53_DUAL_U_DTAG_SPRAM_BANK2_ECC_SVBUS_ENABLE_SET | R/W1TS | 0h | Interrupt Enable Set Register for cpu1_a53_dual_u_dtag_spram_bank2_ecc_svbus_pend |
15 | CPU1_A53_DUAL_U_DTAG_SPRAM_BANK1_ECC_SVBUS_ENABLE_SET | R/W1TS | 0h | Interrupt Enable Set Register for cpu1_a53_dual_u_dtag_spram_bank1_ecc_svbus_pend |
14 | CPU1_A53_DUAL_U_DTAG_SPRAM_BANK0_ECC_SVBUS_ENABLE_SET | R/W1TS | 0h | Interrupt Enable Set Register for cpu1_a53_dual_u_dtag_spram_bank0_ecc_svbus_pend |
13 | CPU1_A53_DUAL_U_DDATA_SPRAM_BANK7_ECC_SVBUS_ENABLE_SET | R/W1TS | 0h | Interrupt Enable Set Register for cpu1_a53_dual_u_ddata_spram_bank7_ecc_svbus_pend |
12 | CPU1_A53_DUAL_U_DDATA_SPRAM_BANK6_ECC_SVBUS_ENABLE_SET | R/W1TS | 0h | Interrupt Enable Set Register for cpu1_a53_dual_u_ddata_spram_bank6_ecc_svbus_pend |
11 | CPU1_A53_DUAL_U_DDATA_SPRAM_BANK5_ECC_SVBUS_ENABLE_SET | R/W1TS | 0h | Interrupt Enable Set Register for cpu1_a53_dual_u_ddata_spram_bank5_ecc_svbus_pend |
10 | CPU1_A53_DUAL_U_DDATA_SPRAM_BANK4_ECC_SVBUS_ENABLE_SET | R/W1TS | 0h | Interrupt Enable Set Register for cpu1_a53_dual_u_ddata_spram_bank4_ecc_svbus_pend |
9 | CPU1_A53_DUAL_U_DDATA_SPRAM_BANK3_ECC_SVBUS_ENABLE_SET | R/W1TS | 0h | Interrupt Enable Set Register for cpu1_a53_dual_u_ddata_spram_bank3_ecc_svbus_pend |
8 | CPU1_A53_DUAL_U_DDATA_SPRAM_BANK2_ECC_SVBUS_ENABLE_SET | R/W1TS | 0h | Interrupt Enable Set Register for cpu1_a53_dual_u_ddata_spram_bank2_ecc_svbus_pend |
7 | CPU1_A53_DUAL_U_DDATA_SPRAM_BANK1_ECC_SVBUS_ENABLE_SET | R/W1TS | 0h | Interrupt Enable Set Register for cpu1_a53_dual_u_ddata_spram_bank1_ecc_svbus_pend |
6 | CPU1_A53_DUAL_U_DDATA_SPRAM_BANK0_ECC_SVBUS_ENABLE_SET | R/W1TS | 0h | Interrupt Enable Set Register for cpu1_a53_dual_u_ddata_spram_bank0_ecc_svbus_pend |
5 | CPU1_A53_DUAL_U_ITAG_SPRAM_RAM1_ECC_SVBUS_ENABLE_SET | R/W1TS | 0h | Interrupt Enable Set Register for cpu1_a53_dual_u_itag_spram_ram1_ecc_svbus_pend |
4 | CPU1_A53_DUAL_U_ITAG_SPRAM_RAM0_ECC_SVBUS_ENABLE_SET | R/W1TS | 0h | Interrupt Enable Set Register for cpu1_a53_dual_u_itag_spram_ram0_ecc_svbus_pend |
3 | CPU1_A53_DUAL_U_IDATA_SPRAM_BANK1_HI_ECC_SVBUS_ENABLE_SET | R/W1TS | 0h | Interrupt Enable Set Register for cpu1_a53_dual_u_idata_spram_bank1_hi_ecc_svbus_pend |
2 | CPU1_A53_DUAL_U_IDATA_SPRAM_BANK1_LO_ECC_SVBUS_ENABLE_SET | R/W1TS | 0h | Interrupt Enable Set Register for cpu1_a53_dual_u_idata_spram_bank1_lo_ecc_svbus_pend |
1 | CPU1_A53_DUAL_U_IDATA_SPRAM_BANK0_HI_ECC_SVBUS_ENABLE_SET | R/W1TS | 0h | Interrupt Enable Set Register for cpu1_a53_dual_u_idata_spram_bank0_hi_ecc_svbus_pend |
0 | CPU1_A53_DUAL_U_IDATA_SPRAM_BANK0_LO_ECC_SVBUS_ENABLE_SET | R/W1TS | 0h | Interrupt Enable Set Register for cpu1_a53_dual_u_idata_spram_bank0_lo_ecc_svbus_pend |
Short Description: Interrupt Enable Clear Register 0
Long Description:
Return to Summary Table
Instance Name | Base Address |
---|---|
A53SS0 | 0071 79C0h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | CPU1_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY3_ECC_SVBUS_ENABLE_CLR | CPU1_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY2_ECC_SVBUS_ENABLE_CLR | CPU1_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY1_ECC_SVBUS_ENABLE_CLR | CPU1_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY0_ECC_SVBUS_ENABLE_CLR | CPU1_A53_DUAL_U_TLB_SPRAM_BANK3_ECC_SVBUS_ENABLE_CLR | CPU1_A53_DUAL_U_TLB_SPRAM_BANK2_ECC_SVBUS_ENABLE_CLR | CPU1_A53_DUAL_U_TLB_SPRAM_BANK1_ECC_SVBUS_ENABLE_CLR | CPU1_A53_DUAL_U_TLB_SPRAM_BANK0_ECC_SVBUS_ENABLE_CLR | CPU1_A53_DUAL_U_DDIRTY_SPRAM_ECC_SVBUS_ENABLE_CLR | CPU1_A53_DUAL_U_DTAG_SPRAM_BANK3_ECC_SVBUS_ENABLE_CLR | CPU1_A53_DUAL_U_DTAG_SPRAM_BANK2_ECC_SVBUS_ENABLE_CLR | ||||
NONE | R/W1TC | R/W1TC | R/W1TC | R/W1TC | R/W1TC | R/W1TC | R/W1TC | R/W1TC | R/W1TC | R/W1TC | R/W1TC | ||||
0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CPU1_A53_DUAL_U_DTAG_SPRAM_BANK1_ECC_SVBUS_ENABLE_CLR | CPU1_A53_DUAL_U_DTAG_SPRAM_BANK0_ECC_SVBUS_ENABLE_CLR | CPU1_A53_DUAL_U_DDATA_SPRAM_BANK7_ECC_SVBUS_ENABLE_CLR | CPU1_A53_DUAL_U_DDATA_SPRAM_BANK6_ECC_SVBUS_ENABLE_CLR | CPU1_A53_DUAL_U_DDATA_SPRAM_BANK5_ECC_SVBUS_ENABLE_CLR | CPU1_A53_DUAL_U_DDATA_SPRAM_BANK4_ECC_SVBUS_ENABLE_CLR | CPU1_A53_DUAL_U_DDATA_SPRAM_BANK3_ECC_SVBUS_ENABLE_CLR | CPU1_A53_DUAL_U_DDATA_SPRAM_BANK2_ECC_SVBUS_ENABLE_CLR | CPU1_A53_DUAL_U_DDATA_SPRAM_BANK1_ECC_SVBUS_ENABLE_CLR | CPU1_A53_DUAL_U_DDATA_SPRAM_BANK0_ECC_SVBUS_ENABLE_CLR | CPU1_A53_DUAL_U_ITAG_SPRAM_RAM1_ECC_SVBUS_ENABLE_CLR | CPU1_A53_DUAL_U_ITAG_SPRAM_RAM0_ECC_SVBUS_ENABLE_CLR | CPU1_A53_DUAL_U_IDATA_SPRAM_BANK1_HI_ECC_SVBUS_ENABLE_CLR | CPU1_A53_DUAL_U_IDATA_SPRAM_BANK1_LO_ECC_SVBUS_ENABLE_CLR | CPU1_A53_DUAL_U_IDATA_SPRAM_BANK0_HI_ECC_SVBUS_ENABLE_CLR | CPU1_A53_DUAL_U_IDATA_SPRAM_BANK0_LO_ECC_SVBUS_ENABLE_CLR |
R/W1TC | R/W1TC | R/W1TC | R/W1TC | R/W1TC | R/W1TC | R/W1TC | R/W1TC | R/W1TC | R/W1TC | R/W1TC | R/W1TC | R/W1TC | R/W1TC | R/W1TC | R/W1TC |
0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
RESERVED | NONE | Reserved | ||
26 | CPU1_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY3_ECC_SVBUS_ENABLE_CLR | R/W1TC | 0h | Interrupt Enable Clear Register for cpu1_a53_dual_u_l1d_tagram_spram_way3_ecc_svbus_pend |
25 | CPU1_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY2_ECC_SVBUS_ENABLE_CLR | R/W1TC | 0h | Interrupt Enable Clear Register for cpu1_a53_dual_u_l1d_tagram_spram_way2_ecc_svbus_pend |
24 | CPU1_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY1_ECC_SVBUS_ENABLE_CLR | R/W1TC | 0h | Interrupt Enable Clear Register for cpu1_a53_dual_u_l1d_tagram_spram_way1_ecc_svbus_pend |
23 | CPU1_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY0_ECC_SVBUS_ENABLE_CLR | R/W1TC | 0h | Interrupt Enable Clear Register for cpu1_a53_dual_u_l1d_tagram_spram_way0_ecc_svbus_pend |
22 | CPU1_A53_DUAL_U_TLB_SPRAM_BANK3_ECC_SVBUS_ENABLE_CLR | R/W1TC | 0h | Interrupt Enable Clear Register for cpu1_a53_dual_u_tlb_spram_bank3_ecc_svbus_pend |
21 | CPU1_A53_DUAL_U_TLB_SPRAM_BANK2_ECC_SVBUS_ENABLE_CLR | R/W1TC | 0h | Interrupt Enable Clear Register for cpu1_a53_dual_u_tlb_spram_bank2_ecc_svbus_pend |
20 | CPU1_A53_DUAL_U_TLB_SPRAM_BANK1_ECC_SVBUS_ENABLE_CLR | R/W1TC | 0h | Interrupt Enable Clear Register for cpu1_a53_dual_u_tlb_spram_bank1_ecc_svbus_pend |
19 | CPU1_A53_DUAL_U_TLB_SPRAM_BANK0_ECC_SVBUS_ENABLE_CLR | R/W1TC | 0h | Interrupt Enable Clear Register for cpu1_a53_dual_u_tlb_spram_bank0_ecc_svbus_pend |
18 | CPU1_A53_DUAL_U_DDIRTY_SPRAM_ECC_SVBUS_ENABLE_CLR | R/W1TC | 0h | Interrupt Enable Clear Register for cpu1_a53_dual_u_ddirty_spram_ecc_svbus_pend |
17 | CPU1_A53_DUAL_U_DTAG_SPRAM_BANK3_ECC_SVBUS_ENABLE_CLR | R/W1TC | 0h | Interrupt Enable Clear Register for cpu1_a53_dual_u_dtag_spram_bank3_ecc_svbus_pend |
16 | CPU1_A53_DUAL_U_DTAG_SPRAM_BANK2_ECC_SVBUS_ENABLE_CLR | R/W1TC | 0h | Interrupt Enable Clear Register for cpu1_a53_dual_u_dtag_spram_bank2_ecc_svbus_pend |
15 | CPU1_A53_DUAL_U_DTAG_SPRAM_BANK1_ECC_SVBUS_ENABLE_CLR | R/W1TC | 0h | Interrupt Enable Clear Register for cpu1_a53_dual_u_dtag_spram_bank1_ecc_svbus_pend |
14 | CPU1_A53_DUAL_U_DTAG_SPRAM_BANK0_ECC_SVBUS_ENABLE_CLR | R/W1TC | 0h | Interrupt Enable Clear Register for cpu1_a53_dual_u_dtag_spram_bank0_ecc_svbus_pend |
13 | CPU1_A53_DUAL_U_DDATA_SPRAM_BANK7_ECC_SVBUS_ENABLE_CLR | R/W1TC | 0h | Interrupt Enable Clear Register for cpu1_a53_dual_u_ddata_spram_bank7_ecc_svbus_pend |
12 | CPU1_A53_DUAL_U_DDATA_SPRAM_BANK6_ECC_SVBUS_ENABLE_CLR | R/W1TC | 0h | Interrupt Enable Clear Register for cpu1_a53_dual_u_ddata_spram_bank6_ecc_svbus_pend |
11 | CPU1_A53_DUAL_U_DDATA_SPRAM_BANK5_ECC_SVBUS_ENABLE_CLR | R/W1TC | 0h | Interrupt Enable Clear Register for cpu1_a53_dual_u_ddata_spram_bank5_ecc_svbus_pend |
10 | CPU1_A53_DUAL_U_DDATA_SPRAM_BANK4_ECC_SVBUS_ENABLE_CLR | R/W1TC | 0h | Interrupt Enable Clear Register for cpu1_a53_dual_u_ddata_spram_bank4_ecc_svbus_pend |
9 | CPU1_A53_DUAL_U_DDATA_SPRAM_BANK3_ECC_SVBUS_ENABLE_CLR | R/W1TC | 0h | Interrupt Enable Clear Register for cpu1_a53_dual_u_ddata_spram_bank3_ecc_svbus_pend |
8 | CPU1_A53_DUAL_U_DDATA_SPRAM_BANK2_ECC_SVBUS_ENABLE_CLR | R/W1TC | 0h | Interrupt Enable Clear Register for cpu1_a53_dual_u_ddata_spram_bank2_ecc_svbus_pend |
7 | CPU1_A53_DUAL_U_DDATA_SPRAM_BANK1_ECC_SVBUS_ENABLE_CLR | R/W1TC | 0h | Interrupt Enable Clear Register for cpu1_a53_dual_u_ddata_spram_bank1_ecc_svbus_pend |
6 | CPU1_A53_DUAL_U_DDATA_SPRAM_BANK0_ECC_SVBUS_ENABLE_CLR | R/W1TC | 0h | Interrupt Enable Clear Register for cpu1_a53_dual_u_ddata_spram_bank0_ecc_svbus_pend |
5 | CPU1_A53_DUAL_U_ITAG_SPRAM_RAM1_ECC_SVBUS_ENABLE_CLR | R/W1TC | 0h | Interrupt Enable Clear Register for cpu1_a53_dual_u_itag_spram_ram1_ecc_svbus_pend |
4 | CPU1_A53_DUAL_U_ITAG_SPRAM_RAM0_ECC_SVBUS_ENABLE_CLR | R/W1TC | 0h | Interrupt Enable Clear Register for cpu1_a53_dual_u_itag_spram_ram0_ecc_svbus_pend |
3 | CPU1_A53_DUAL_U_IDATA_SPRAM_BANK1_HI_ECC_SVBUS_ENABLE_CLR | R/W1TC | 0h | Interrupt Enable Clear Register for cpu1_a53_dual_u_idata_spram_bank1_hi_ecc_svbus_pend |
2 | CPU1_A53_DUAL_U_IDATA_SPRAM_BANK1_LO_ECC_SVBUS_ENABLE_CLR | R/W1TC | 0h | Interrupt Enable Clear Register for cpu1_a53_dual_u_idata_spram_bank1_lo_ecc_svbus_pend |
1 | CPU1_A53_DUAL_U_IDATA_SPRAM_BANK0_HI_ECC_SVBUS_ENABLE_CLR | R/W1TC | 0h | Interrupt Enable Clear Register for cpu1_a53_dual_u_idata_spram_bank0_hi_ecc_svbus_pend |
0 | CPU1_A53_DUAL_U_IDATA_SPRAM_BANK0_LO_ECC_SVBUS_ENABLE_CLR | R/W1TC | 0h | Interrupt Enable Clear Register for cpu1_a53_dual_u_idata_spram_bank0_lo_ecc_svbus_pend |
Short Description: AGGR interrupt enable set Register
Long Description:
Return to Summary Table
Instance Name | Base Address |
---|---|
A53SS0 | 0071 7A00h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
NONE | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | TIMEOUT | PARITY | |||||||||||||
NONE | R/W1TS | R/W1TS | |||||||||||||
0 | 0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
RESERVED | NONE | Reserved | ||
1 | TIMEOUT | R/W1TS | 0h | interrupt enable set for svbus timeout errors |
0 | PARITY | R/W1TS | 0h | interrupt enable set for parity errors |
Short Description: AGGR interrupt enable clear Register
Long Description:
Return to Summary Table
Instance Name | Base Address |
---|---|
A53SS0 | 0071 7A04h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
NONE | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | TIMEOUT | PARITY | |||||||||||||
NONE | R/W1TC | R/W1TC | |||||||||||||
0 | 0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
RESERVED | NONE | Reserved | ||
1 | TIMEOUT | R/W1TC | 0h | interrupt enable clear for svbus timeout errors |
0 | PARITY | R/W1TC | 0h | interrupt enable clear for parity errors |
Short Description: AGGR interrupt status set Register
Long Description:
Return to Summary Table
Instance Name | Base Address |
---|---|
A53SS0 | 0071 7A08h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
NONE | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | TIMEOUT | PARITY | |||||||||||||
NONE | R/WI | R/WI | |||||||||||||
0 | 0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
RESERVED | NONE | Reserved | ||
3 - 2 | TIMEOUT | R/WI | 0h | interrupt status set for svbus timeout errors |
1 - 0 | PARITY | R/WI | 0h | interrupt status set for parity errors |
Short Description: AGGR interrupt status clear Register
Long Description:
Return to Summary Table
Instance Name | Base Address |
---|---|
A53SS0 | 0071 7A0Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
NONE | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | TIMEOUT | PARITY | |||||||||||||
NONE | R/WD | R/WD | |||||||||||||
0 | 0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
RESERVED | NONE | Reserved | ||
3 - 2 | TIMEOUT | R/WD | 0h | interrupt status clear for svbus timeout errors |
1 - 0 | PARITY | R/WD | 0h | interrupt status clear for parity errors |
Access Type | Code | Description |
---|---|---|
R | R | Read |
R/W1TC | R/W1TC | Read/Write 1 To Clear |
R/W | R/W | Read / Write |
R/W1TS | R/W1TS | Read/Write 1 To Set |
R/WI | R/WI | Read/Write Increment. A write to this bit field increments the specified register bit field by the amount written. |
R/WD | R/WD | Read/Write Decrement. A write to this bit field decrements the specified register bit field by the amount written. |