When the receiver FIFO is enabled in the FIFO control register (via setting the UART_INT_FIFO[0] IIR_IPEND to 1h) and the receiver interrupts are disabled in the interrupt enable register (UART_INT_EN), the poll mode is selected for the receiver FIFO. Similarly, when the transmitter FIFO is enabled via setting the same bit (UART_INT_FIFO[0] IIR_IPEND to 1h) and the transmitter interrupts are disabled, the transmitted FIFO is in the poll mode. In the poll mode, the CPU detects events by checking bits in the line status register - UART_LSR1:
- The UART_LSR1[7] RXFIFOE bit indicates whether there are any errors in the receiver FIFO.
- The UART_LSR1[6] TEMT bit indicates that both the transmitter holding register (THR) and the transmitter shift register (TSR) are empty.
- The UART_LSR1[5] THRE bit indicates when THR ( mapped in the UART_RBR_TBR[7-0] RBR_DATA bitfield ) is empty.
- The following line status register - UART_LSR1 bits specify which error or errors have occurred:
- The UART_LSR1[0] DR (data-ready) bit is set as long as there is at least one byte in the receiver FIFO.
Also, in the FIFO poll mode:
- The interrupt identification ([3-1] IIR_INTID) bit field in register UART_INT_FIFO are not affected by any events because the interrupts are disabled.
- The PRU_ICSSG UART0 does not indicate when the receiver FIFO trigger level is reached or when a receiver time-out occurs.