SPRUIM2H May 2020 – October 2023 AM2431 , AM2432 , AM2434 , AM6411 , AM6412 , AM6421 , AM6422 , AM6441 , AM6442
There is one DCC module integrated in the device MCU domain - MCU_DCC0. Figure 12-2503 shows the integration of MCU_DCC module.
Table 12-4781 through Table 12-4784 summarize the integration of DCC in the device MCU domain.
Module Instance | Power Sleep Controller | Power Domain | Module Domain | Interconnect |
---|---|---|---|---|
MCU_DCC0 | WKUP_PSC0 | PD0 | LPSC0 | MCU_CBASS0 |
MCU_DCC1 | WKUP_PSC0 | PD0 | LPSC0 | MCU_CBASS0 |
MCU_DCC2 | WKUP_PSC0 | PD0 | LPSC0 | MCU_CBASS0 |
Module Instance | Module Clock Input | Source Clock Signal | Source | Description |
---|---|---|---|---|
MCU_DCC0 | MCU_DCC0_FICLK | MCU_SYSCLK0/4 | WKUP_PLLCTRL0 | MCU_DCC0 interface and functional clock |
Module Instance | Module Reset Input | Source Reset Signal | Source | Description |
---|---|---|---|---|
MCU_DCC0 | MCU_DCC0_RST | MOD_G_RST | LPSC0 | MCU_DCC0 asynchronous module reset |
Module Instance | Module Interrupt Signal | Destination Interrupt Input | Destination | Description | Type |
---|---|---|---|---|---|
MCU_DCC0 | MCU_DCC0_INTR_DONE_LEVEL_0 | MCU_DCC0 one-shot mode complete interrupt | Level | ||
MCU_DCC0 one-shot mode complete interrupt | Level | ||||
MCU_DCC0 one-shot mode complete interrupt | Level | ||||
MCU_DCC0 one-shot mode complete interrupt | Level | ||||
MCU_DCC0 one-shot mode complete interrupt | Level | ||||
MCU_DCC0_INTR_ERR_LEVEL_0 | MCU_DCC0 error interrupt | Level |
For more information on the interconnects, see Chapter 3, System Interconnect.
For more information on the power, reset and clock management, see the corresponding sections within Chapter 5, Device Configuration.
For more information on the device interrupt controllers, see Section 9.2, Interrupt Controllers.
Section 12.6.1.2.1.1 summarizes the DCC input source clocks in the device MCU domain.