SPRUIM2H May 2020 – October 2023 AM2431 , AM2432 , AM2434 , AM6411 , AM6412 , AM6421 , AM6422 , AM6441 , AM6442
Table 12-1417 lists the memory-mapped registers for the CPSW0_ECC registers. All register offset addresses not listed in Table 12-1417 should be considered as reserved locations and the register contents should not be modified.
Instance | Base Address |
---|---|
CPSW0_ECC | 0070 4000h |
Offset(1) | Acronym | Register Name | CPSW0_ECC Physical Address |
---|---|---|---|
0h | CPSW_ECC_REV | Aggregator Revision Register | 0070 4000h |
8h | CPSW_ECC_VECTOR | ECC Vector Register | 0070 4008h |
Ch | CPSW_ECC_STAT | Misc Status | 0070 400Ch |
10h + formula | CPSW_ECC_RESERVED_SVBUS_y | Reserved Area for Serial VBUS Registers | 0070 4010h + formula |
3Ch | CPSW_ECC_SEC_EOI_REG | EOI Register | 0070 403Ch |
40h | CPSW_ECC_SEC_STATUS_REG0 | Interrupt Status Register 0 | 0070 4040h |
80h | CPSW_ECC_SEC_ENABLE_SET_REG0 | Interrupt Enable Set Register 0 | 0070 4080h |
C0h | CPSW_ECC_SEC_ENABLE_CLR_REG0 | Interrupt Enable Clear Register 0 | 0070 40C0h |
13Ch | CPSW_ECC_DED_EOI_REG | EOI Register | 0070 413Ch |
140h | CPSW_ECC_DED_STATUS_REG0 | Interrupt Status Register 0 | 0070 4140h |
180h | CPSW_ECC_DED_ENABLE_SET_REG0 | Interrupt Enable Set Register 0 | 0070 4180h |
1C0h | CPSW_ECC_DED_ENABLE_CLR_REG0 | Interrupt Enable Clear Register 0 | 0070 41C0h |
200h | CPSW_ECC_AGGR_ENABLE_SET | AGGR interrupt enable set Register | 0070 4200h |
204h | CPSW_ECC_AGGR_ENABLE_CLR | AGGR interrupt enable clear Register | 0070 4204h |
208h | CPSW_ECC_AGGR_STATUS_SET | AGGR interrupt status set Register | 0070 4208h |
20Ch | CPSW_ECC_AGGR_STATUS_CLR | AGGR interrupt status clear Register | 0070 420Ch |
CPSW_ECC_REV is shown in Figure 12-731 and described in Table 12-1419.
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Revision parameters.
Instance | Physical Address |
---|---|
CPSW0_ECC | 0070 4000h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
SCHEME | BU | MODULE_ID | |||||||||||||
R-1h | R-2h | R-6A0h | |||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
REVRTL | REVMAJ | CUSTOM | REVMIN | ||||||||||||
R-4h | R-2h | R-0h | R-1h | ||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-30 | SCHEME | R | 1h | Scheme |
29-28 | BU | R | 2h | bu |
27-16 | MODULE_ID | R | 6A0h | Module ID |
15-11 | REVRTL | R | 4h | RTL version |
10-8 | REVMAJ | R | 2h | Major version |
7-6 | CUSTOM | R | 0h | Custom version |
5-0 | REVMIN | R | 1h | Minor version |
CPSW_ECC_VECTOR is shown in Figure 12-732 and described in Table 12-1421.
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ECC Vector Register.
Instance | Physical Address |
---|---|
CPSW0_ECC | 0070 4008h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | RD_SVBUS_DONE | ||||||
R/W-X | R/W1C-0h | ||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RD_SVBUS_ADDRESS | |||||||
R/W-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RD_SVBUS | RESERVED | ECC_VECTOR | |||||
R/W1S-0h | R/W-X | R/W-0h | |||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ECC_VECTOR | |||||||
R/W-0h | |||||||
LEGEND: R/W = Read/Write; R/W1C = Read/Write 1 to Clear Bit; R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-25 | RESERVED | R/W | X | |
24 | RD_SVBUS_DONE | R/W1C | 0h | Status to indicate if read on serial VBUS is complete, write of any value will clear this bit. |
23-16 | RD_SVBUS_ADDRESS | R/W | 0h | Read address. |
15 | RD_SVBUS | R/W1S | 0h | Write 1 to trigger a read on the serial VBUS. |
14-11 | RESERVED | R/W | X | |
10-0 | ECC_VECTOR | R/W | 0h | Value written to select the corresponding ECC RAM for control or status. |
CPSW_ECC_STAT is shown in Figure 12-733 and described in Table 12-1423.
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Misc Status.
Instance | Physical Address |
---|---|
CPSW0_ECC | 0070 400Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | NUM_RAMS | ||||||||||||||||||||||||||||||
R-X | R-14h | ||||||||||||||||||||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-11 | RESERVED | R | X | |
10-0 | NUM_RAMS | R | 14h | Indicates the number of RAMS serviced by the ECC aggregator. |
CPSW_ECC_RESERVED_SVBUS_y is shown in Figure 12-734 and described in Table 12-1425.
Return to Summary Table.
Reference other documents that contain the ECC RAM wrapper and EDC controller serial vbus register sets.
Offset = 10h + (y * 4h); where y = 0h to 7h
Instance | Physical Address |
---|---|
CPSW0_ECC | 0070 4010h + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DATA | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | DATA | R/W | 0h | Serial VBUS register data. |
CPSW_ECC_SEC_EOI_REG is shown in Figure 12-735 and described in Table 12-1427.
Return to Summary Table.
EOI Register.
The EOI register is used to re-trigger the pulse interrupt signal to ensure that any nested interrupt events are serviced. The software interrupt handler must write to the EOI register at the end of the current interrupt processing routine, so that new events can re-trigger the pulse interrupt signal again. For level interrupt signals the EOI register is not functional and must not be used.
Instance | Physical Address |
---|---|
CPSW0_ECC | 0070 403Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R/W-X | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R/W-X | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R/W-X | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | EOI_WR | ||||||
R/W-X | R/W1S-0h | ||||||
LEGEND: R/W = Read/Write; R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-1 | RESERVED | R/W | X | |
0 | EOI_WR | R/W1S | 0h | EOI Register. |
CPSW_ECC_SEC_STATUS_REG0 is shown in Figure 12-736 and described in Table 12-1429.
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Interrupt Status Register 0.
Instance | Physical Address |
---|---|
CPSW0_ECC | 0070 4040h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R/W-X | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | RAMECC19_PEND | RAMECC18_PEND | RAMECC17_PEND | RAMECC16_PEND | |||
R/W-X | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | |||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RAMECC15_PEND | RAMECC14_PEND | RAMECC13_PEND | RAMECC12_PEND | RAMECC11_PEND | RAMECC10_PEND | RAMECC9_PEND | RAMECC8_PEND |
R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RAMECC7_PEND | RAMECC6_PEND | RAMECC5_PEND | RAMECC4_PEND | RAMECC3_PEND | RAMECC2_PEND | RAMECC1_PEND | RAMECC0_PEND |
R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h |
LEGEND: R/W = Read/Write; R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-20 | RESERVED | R/W | X | |
19 | RAMECC19_PEND | R/W1S | 0h | Interrupt Pending Status for ramecc19_pend. |
18 | RAMECC18_PEND | R/W1S | 0h | Interrupt Pending Status for ramecc18_pend. |
17 | RAMECC17_PEND | R/W1S | 0h | Interrupt Pending Status for ramecc17_pend. |
16 | RAMECC16_PEND | R/W1S | 0h | Interrupt Pending Status for ramecc16_pend. |
15 | RAMECC15_PEND | R/W1S | 0h | Interrupt Pending Status for ramecc15_pend. |
14 | RAMECC14_PEND | R/W1S | 0h | Interrupt Pending Status for ramecc14_pend. |
13 | RAMECC13_PEND | R/W1S | 0h | Interrupt Pending Status for ramecc13_pend. |
12 | RAMECC12_PEND | R/W1S | 0h | Interrupt Pending Status for ramecc12_pend. |
11 | RAMECC11_PEND | R/W1S | 0h | Interrupt Pending Status for ramecc11_pend. |
10 | RAMECC10_PEND | R/W1S | 0h | Interrupt Pending Status for ramecc10_pend. |
9 | RAMECC9_PEND | R/W1S | 0h | Interrupt Pending Status for ramecc9_pend. |
8 | RAMECC8_PEND | R/W1S | 0h | Interrupt Pending Status for ramecc8_pend. |
7 | RAMECC7_PEND | R/W1S | 0h | Interrupt Pending Status for ramecc7_pend. |
6 | RAMECC6_PEND | R/W1S | 0h | Interrupt Pending Status for ramecc6_pend. |
5 | RAMECC5_PEND | R/W1S | 0h | Interrupt Pending Status for ramecc5_pend. |
4 | RAMECC4_PEND | R/W1S | 0h | Interrupt Pending Status for ramecc4_pend. |
3 | RAMECC3_PEND | R/W1S | 0h | Interrupt Pending Status for ramecc3_pend. |
2 | RAMECC2_PEND | R/W1S | 0h | Interrupt Pending Status for ramecc2_pend. |
1 | RAMECC1_PEND | R/W1S | 0h | Interrupt Pending Status for ramecc1_pend. |
0 | RAMECC0_PEND | R/W1S | 0h | Interrupt Pending Status for ramecc0_pend. |
CPSW_ECC_SEC_ENABLE_SET_REG0 is shown in Figure 12-737 and described in Table 12-1431.
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Interrupt Enable Set Register 0.
Instance | Physical Address |
---|---|
CPSW0_ECC | 0070 4080h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R/W-X | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | RAMECC19_ENABLE_SET | RAMECC18_ENABLE_SET | RAMECC17_ENABLE_SET | RAMECC16_ENABLE_SET | |||
R/W-X | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | |||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RAMECC15_ENABLE_SET | RAMECC14_ENABLE_SET | RAMECC13_ENABLE_SET | RAMECC12_ENABLE_SET | RAMECC11_ENABLE_SET | RAMECC10_ENABLE_SET | RAMECC9_ENABLE_SET | RAMECC8_ENABLE_SET |
R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RAMECC7_ENABLE_SET | RAMECC6_ENABLE_SET | RAMECC5_ENABLE_SET | RAMECC4_ENABLE_SET | RAMECC3_ENABLE_SET | RAMECC2_ENABLE_SET | RAMECC1_ENABLE_SET | RAMECC0_ENABLE_SET |
R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h |
LEGEND: R/W = Read/Write; R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-20 | RESERVED | R/W | X | |
19 | RAMECC19_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for ramecc19_pend. |
18 | RAMECC18_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for ramecc18_pend. |
17 | RAMECC17_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for ramecc17_pend. |
16 | RAMECC16_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for ramecc16_pend. |
15 | RAMECC15_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for ramecc15_pend. |
14 | RAMECC14_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for ramecc14_pend. |
13 | RAMECC13_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for ramecc13_pend. |
12 | RAMECC12_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for ramecc12_pend. |
11 | RAMECC11_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for ramecc11_pend. |
10 | RAMECC10_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for ramecc10_pend. |
9 | RAMECC9_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for ramecc9_pend. |
8 | RAMECC8_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for ramecc8_pend. |
7 | RAMECC7_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for ramecc7_pend. |
6 | RAMECC6_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for ramecc6_pend. |
5 | RAMECC5_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for ramecc5_pend. |
4 | RAMECC4_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for ramecc4_pend. |
3 | RAMECC3_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for ramecc3_pend. |
2 | RAMECC2_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for ramecc2_pend. |
1 | RAMECC1_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for ramecc1_pend. |
0 | RAMECC0_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for ramecc0_pend. |
CPSW_ECC_SEC_ENABLE_CLR_REG0 is shown in Figure 12-738 and described in Table 12-1433.
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Interrupt Enable Clear Register 0.
Instance | Physical Address |
---|---|
CPSW0_ECC | 0070 40C0h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R/W-X | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | RAMECC19_ENABLE_CLR | RAMECC18_ENABLE_CLR | RAMECC17_ENABLE_CLR | RAMECC16_ENABLE_CLR | |||
R/W-X | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | |||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RAMECC15_ENABLE_CLR | RAMECC14_ENABLE_CLR | RAMECC13_ENABLE_CLR | RAMECC12_ENABLE_CLR | RAMECC11_ENABLE_CLR | RAMECC10_ENABLE_CLR | RAMECC9_ENABLE_CLR | RAMECC8_ENABLE_CLR |
R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RAMECC7_ENABLE_CLR | RAMECC6_ENABLE_CLR | RAMECC5_ENABLE_CLR | RAMECC4_ENABLE_CLR | RAMECC3_ENABLE_CLR | RAMECC2_ENABLE_CLR | RAMECC1_ENABLE_CLR | RAMECC0_ENABLE_CLR |
R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h |
LEGEND: R/W = Read/Write; R/W1C = Read/Write 1 to Clear Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-20 | RESERVED | R/W | X | |
19 | RAMECC19_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for ramecc19_pend. |
18 | RAMECC18_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for ramecc18_pend. |
17 | RAMECC17_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for ramecc17_pend. |
16 | RAMECC16_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for ramecc16_pend. |
15 | RAMECC15_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for ramecc15_pend. |
14 | RAMECC14_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for ramecc14_pend. |
13 | RAMECC13_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for ramecc13_pend. |
12 | RAMECC12_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for ramecc12_pend. |
11 | RAMECC11_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for ramecc11_pend. |
10 | RAMECC10_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for ramecc10_pend. |
9 | RAMECC9_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for ramecc9_pend. |
8 | RAMECC8_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for ramecc8_pend. |
7 | RAMECC7_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for ramecc7_pend. |
6 | RAMECC6_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for ramecc6_pend. |
5 | RAMECC5_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for ramecc5_pend. |
4 | RAMECC4_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for ramecc4_pend. |
3 | RAMECC3_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for ramecc3_pend. |
2 | RAMECC2_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for ramecc2_pend. |
1 | RAMECC1_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for ramecc1_pend. |
0 | RAMECC0_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for ramecc0_pend. |
CPSW_ECC_DED_EOI_REG is shown in Figure 12-739 and described in Table 12-1435.
Return to Summary Table.
EOI Register.
The EOI register is used to re-trigger the pulse interrupt signal to ensure that any nested interrupt events are serviced. The software interrupt handler must write to the EOI register at the end of the current interrupt processing routine, so that new events can re-trigger the pulse interrupt signal again. For level interrupt signals the EOI register is not functional and must not be used.
Instance | Physical Address |
---|---|
CPSW0_ECC | 0070 413Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R/W-X | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R/W-X | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R/W-X | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | EOI_WR | ||||||
R/W-X | R/W1S-0h | ||||||
LEGEND: R/W = Read/Write; R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-1 | RESERVED | R/W | X | |
0 | EOI_WR | R/W1S | 0h | EOI Register. |
CPSW_ECC_DED_STATUS_REG0 is shown in Figure 12-740 and described in Table 12-1437.
Return to Summary Table.
Interrupt Status Register 0.
Instance | Physical Address |
---|---|
CPSW0_ECC | 0070 4140h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R/W-X | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | RAMECC19_PEND | RAMECC18_PEND | RAMECC17_PEND | RAMECC16_PEND | |||
R/W-X | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | |||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RAMECC15_PEND | RAMECC14_PEND | RAMECC13_PEND | RAMECC12_PEND | RAMECC11_PEND | RAMECC10_PEND | RAMECC9_PEND | RAMECC8_PEND |
R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RAMECC7_PEND | RAMECC6_PEND | RAMECC5_PEND | RAMECC4_PEND | RAMECC3_PEND | RAMECC2_PEND | RAMECC1_PEND | RAMECC0_PEND |
R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h |
LEGEND: R/W = Read/Write; R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-20 | RESERVED | R/W | X | |
19 | RAMECC19_PEND | R/W1S | 0h | Interrupt Pending Status for ramecc19_pend. |
18 | RAMECC18_PEND | R/W1S | 0h | Interrupt Pending Status for ramecc18_pend. |
17 | RAMECC17_PEND | R/W1S | 0h | Interrupt Pending Status for ramecc17_pend. |
16 | RAMECC16_PEND | R/W1S | 0h | Interrupt Pending Status for ramecc16_pend. |
15 | RAMECC15_PEND | R/W1S | 0h | Interrupt Pending Status for ramecc15_pend. |
14 | RAMECC14_PEND | R/W1S | 0h | Interrupt Pending Status for ramecc14_pend. |
13 | RAMECC13_PEND | R/W1S | 0h | Interrupt Pending Status for ramecc13_pend. |
12 | RAMECC12_PEND | R/W1S | 0h | Interrupt Pending Status for ramecc12_pend. |
11 | RAMECC11_PEND | R/W1S | 0h | Interrupt Pending Status for ramecc11_pend. |
10 | RAMECC10_PEND | R/W1S | 0h | Interrupt Pending Status for ramecc10_pend. |
9 | RAMECC9_PEND | R/W1S | 0h | Interrupt Pending Status for ramecc9_pend. |
8 | RAMECC8_PEND | R/W1S | 0h | Interrupt Pending Status for ramecc8_pend. |
7 | RAMECC7_PEND | R/W1S | 0h | Interrupt Pending Status for ramecc7_pend. |
6 | RAMECC6_PEND | R/W1S | 0h | Interrupt Pending Status for ramecc6_pend. |
5 | RAMECC5_PEND | R/W1S | 0h | Interrupt Pending Status for ramecc5_pend. |
4 | RAMECC4_PEND | R/W1S | 0h | Interrupt Pending Status for ramecc4_pend. |
3 | RAMECC3_PEND | R/W1S | 0h | Interrupt Pending Status for ramecc3_pend. |
2 | RAMECC2_PEND | R/W1S | 0h | Interrupt Pending Status for ramecc2_pend. |
1 | RAMECC1_PEND | R/W1S | 0h | Interrupt Pending Status for ramecc1_pend. |
0 | RAMECC0_PEND | R/W1S | 0h | Interrupt Pending Status for ramecc0_pend. |
CPSW_ECC_DED_ENABLE_SET_REG0 is shown in Figure 12-741 and described in Table 12-1439.
Return to Summary Table.
Interrupt Enable Set Register 0.
Instance | Physical Address |
---|---|
CPSW0_ECC | 0070 4180h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R/W-X | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | RAMECC19_ENABLE_SET | RAMECC18_ENABLE_SET | RAMECC17_ENABLE_SET | RAMECC16_ENABLE_SET | |||
R/W-X | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | |||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RAMECC15_ENABLE_SET | RAMECC14_ENABLE_SET | RAMECC13_ENABLE_SET | RAMECC12_ENABLE_SET | RAMECC11_ENABLE_SET | RAMECC10_ENABLE_SET | RAMECC9_ENABLE_SET | RAMECC8_ENABLE_SET |
R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RAMECC7_ENABLE_SET | RAMECC6_ENABLE_SET | RAMECC5_ENABLE_SET | RAMECC4_ENABLE_SET | RAMECC3_ENABLE_SET | RAMECC2_ENABLE_SET | RAMECC1_ENABLE_SET | RAMECC0_ENABLE_SET |
R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h |
LEGEND: R/W = Read/Write; R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-20 | RESERVED | R/W | X | |
19 | RAMECC19_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for ramecc19_pend. |
18 | RAMECC18_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for ramecc18_pend. |
17 | RAMECC17_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for ramecc17_pend. |
16 | RAMECC16_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for ramecc16_pend. |
15 | RAMECC15_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for ramecc15_pend. |
14 | RAMECC14_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for ramecc14_pend. |
13 | RAMECC13_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for ramecc13_pend. |
12 | RAMECC12_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for ramecc12_pend. |
11 | RAMECC11_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for ramecc11_pend. |
10 | RAMECC10_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for ramecc10_pend. |
9 | RAMECC9_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for ramecc9_pend. |
8 | RAMECC8_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for ramecc8_pend. |
7 | RAMECC7_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for ramecc7_pend. |
6 | RAMECC6_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for ramecc6_pend. |
5 | RAMECC5_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for ramecc5_pend. |
4 | RAMECC4_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for ramecc4_pend. |
3 | RAMECC3_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for ramecc3_pend. |
2 | RAMECC2_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for ramecc2_pend. |
1 | RAMECC1_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for ramecc1_pend. |
0 | RAMECC0_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for ramecc0_pend. |
CPSW_ECC_DED_ENABLE_CLR_REG0 is shown in Figure 12-742 and described in Table 12-1441.
Return to Summary Table.
Interrupt Enable Clear Register 0.
Instance | Physical Address |
---|---|
CPSW0_ECC | 0070 41C0h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R/W-X | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | RAMECC19_ENABLE_CLR | RAMECC18_ENABLE_CLR | RAMECC17_ENABLE_CLR | RAMECC16_ENABLE_CLR | |||
R/W-X | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | |||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RAMECC15_ENABLE_CLR | RAMECC14_ENABLE_CLR | RAMECC13_ENABLE_CLR | RAMECC12_ENABLE_CLR | RAMECC11_ENABLE_CLR | RAMECC10_ENABLE_CLR | RAMECC9_ENABLE_CLR | RAMECC8_ENABLE_CLR |
R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RAMECC7_ENABLE_CLR | RAMECC6_ENABLE_CLR | RAMECC5_ENABLE_CLR | RAMECC4_ENABLE_CLR | RAMECC3_ENABLE_CLR | RAMECC2_ENABLE_CLR | RAMECC1_ENABLE_CLR | RAMECC0_ENABLE_CLR |
R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h |
LEGEND: R/W = Read/Write; R/W1C = Read/Write 1 to Clear Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-20 | RESERVED | R/W | X | |
19 | RAMECC19_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for ramecc19_pend. |
18 | RAMECC18_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for ramecc18_pend. |
17 | RAMECC17_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for ramecc17_pend. |
16 | RAMECC16_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for ramecc16_pend. |
15 | RAMECC15_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for ramecc15_pend. |
14 | RAMECC14_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for ramecc14_pend. |
13 | RAMECC13_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for ramecc13_pend. |
12 | RAMECC12_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for ramecc12_pend |
11 | RAMECC11_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for ramecc11_pend. |
10 | RAMECC10_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for ramecc10_pend. |
9 | RAMECC9_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for ramecc9_pend. |
8 | RAMECC8_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for ramecc8_pend. |
7 | RAMECC7_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for ramecc7_pend. |
6 | RAMECC6_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for ramecc6_pend. |
5 | RAMECC5_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for ramecc5_pend. |
4 | RAMECC4_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for ramecc4_pend. |
3 | RAMECC3_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for ramecc3_pend. |
2 | RAMECC2_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for ramecc2_pend. |
1 | RAMECC1_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for ramecc1_pend. |
0 | RAMECC0_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for ramecc0_pend. |
CPSW_ECC_AGGR_ENABLE_SET is shown in Figure 12-743 and described in Table 12-1443.
Return to Summary Table.
AGGR interrupt enable set Register.
Instance | Physical Address |
---|---|
CPSW0_ECC | 0070 4200h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R/W-X | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R/W-X | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R/W-X | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | TIMEOUT | PARITY | |||||
R/W-X | R/W1S-0h | R/W1S-0h | |||||
LEGEND: R/W = Read/Write; R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-2 | RESERVED | R/W | X | |
1 | TIMEOUT | R/W1S | 0h | Interrupt enable set for SVBUS timeout errors. |
0 | PARITY | R/W1S | 0h | Interrupt enable set for parity errors. |
CPSW_ECC_AGGR_ENABLE_CLR is shown in Figure 12-744 and described in Table 12-1445.
Return to Summary Table.
AGGR interrupt enable clear Register.
Instance | Physical Address |
---|---|
CPSW0_ECC | 0070 4204h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R/W-X | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R/W-X | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R/W-X | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | TIMEOUT | PARITY | |||||
R/W-X | R/W1C-0h | R/W1C-0h | |||||
LEGEND: R/W = Read/Write; R/W1C = Read/Write 1 to Clear Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-2 | RESERVED | R/W | X | |
1 | TIMEOUT | R/W1C | 0h | Interrupt enable clear for SVBUS timeout errors. |
0 | PARITY | R/W1C | 0h | Interrupt enable clear for parity errors. |
CPSW_ECC_AGGR_STATUS_SET is shown in Figure 12-745 and described in Table 12-1447.
Return to Summary Table.
AGGR interrupt status set Register.
Instance | Physical Address |
---|---|
CPSW0_ECC | 0070 4208h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R/W-X | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R/W-X | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R/W-X | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | TIMEOUT | PARITY | |||||
R/W-X | R/Wincr-0h | R/Wincr-0h | |||||
LEGEND: R/W = Read/Write; R/Wincr = Read/Write to Increment Field; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-4 | RESERVED | R/W | X | |
3-2 | TIMEOUT | R/Wincr | 0h | Interrupt status set for SVBUS timeout errors. |
1-0 | PARITY | R/Wincr | 0h | Interrupt status set for parity errors. |
CPSW_ECC_AGGR_STATUS_CLR is shown in Figure 12-746 and described in Table 12-1449.
Return to Summary Table.
AGGR interrupt status clear Register.
Instance | Physical Address |
---|---|
CPSW0_ECC | 0070 420Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R/W-X | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R/W-X | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R/W-X | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | TIMEOUT | PARITY | |||||
R/W-X | R/Wdecr-0h | R/Wdecr-0h | |||||
LEGEND: R/W = Read/Write; R/Wdecr = Read/Write to Decrement Field; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-4 | RESERVED | R/W | X | |
3-2 | TIMEOUT | R/Wdecr | 0h | Interrupt status clear for SVBUS timeout errors. |
1-0 | PARITY | R/Wdecr | 0h | Interrupt status clear for parity errors. |