SPRUIM2 User guide

SPRUIM2H May 2020 – October 2023 AM2431 , AM2432 , AM2434 , AM6411 , AM6412 , AM6421 , AM6422 , AM6441 , AM6442

12.4.4.5 EQEP Registers

Table 12-4411 lists the memory-mapped registers for the EQEP modules. All register offset addresses not listed in Table 12-4411 should be considered as reserved locations and the register contents should not be modified.

Table 12-4410 EQEP Instances

Instance	Base Address
EQEP0_REG	2320 0000h
EQEP1_REG	2321 0000h
EQEP2_REG	2322 0000h

Table 12-4411 EQEP Registers

Offset	Acronym	Register Name	EQEP0_REG Physical Address	EQEP1_REG Physical Address	EQEP2_REG Physical Address
0h	EQEP_QPOSCNT	QEP Position Counter Register	2320 0000h	2321 0000h	2322 0000h
4h	EQEP_QPOSINIT	Position Counter Initialization Register	2320 0004h	2321 0004h	2322 0004h
8h	EQEP_QPOSMAX	Maximum Position Count Register	2320 0008h	2321 0008h	2322 0008h
Ch	EQEP_QPOSCMP	Position Compare Register	2320 000Ch	2321 000Ch	2322 000Ch
10h	EQEP_QPOSILAT	Index Position Latch Register	2320 0010h	2321 0010h	2322 0010h
14h	EQEP_QPOSSLAT	Strobe Position Latch Register	2320 0014h	2321 0014h	2322 0014h
18h	EQEP_QPOSLAT	QEP Position Counter Latch Register	2320 0018h	2321 0018h	2322 0018h
1Ch	EQEP_QUTMR	QEP Unit Timer Register	2320 001Ch	2321 001Ch	2322 001Ch
20h	EQEP_QUPRD	QEP Unit Period Register	2320 0020h	2321 0020h	2322 0020h
24h	EQEP_QWD_TMR_PRD	QEP Watchdog Timer and Period Register	2320 0024h	2321 0024h	2322 0024h
28h	EQEP_QDEC_QEP_CTL	Quadrature Decoder and QEP Control Register	2320 0028h	2321 0028h	2322 0028h
2Ch	EQEP_QCAP_QPOS_CTL	QEP Capture and Position Compare Control Register	2320 002Ch	2321 002Ch	2322 002Ch
30h	EQEP_QINT_EN_FLG	QEP Interrupt Control and Flag Register	2320 0030h	2321 0030h	2322 0030h
34h	EQEP_QINT_CLR_FRC	QEP Interrupt Clear and Forcing Register	2320 0034h	2321 0034h	2322 0034h
38h	EQEP_QEP_STS_CT	QEP Status and Capture Timer Register	2320 0038h	2321 0038h	2322 0038h
3Ch	EQEP_QC_PRD_TLAT	QEP Capture Period and Timer Latch Register	2320 003Ch	2321 003Ch	2322 003Ch
40h	EQEP_QCPRDLAT	QEP Capture Period Latch Register	2320 0040h	2321 0040h	2322 0040h
5Ch	EQEP_PID	Peripheral ID Register	2320 005Ch	2321 005Ch	2322 005Ch

4.4.5.1 EQEP_QPOSCNT Register (Offset = 0h) [reset = 0h]

EQEP_QPOSCNT is shown in Figure 12-2326 and described in Table 12-4413.

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QEP Position Counter register

Table 12-4412 EQEP_QPOSCNT Instances

Instance	Physical Address
EQEP0_REG	2320 0000h
EQEP1_REG	2321 0000h
EQEP2_REG	2322 0000h

Figure 12-2326 EQEP_QPOSCNT Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
POSCNT
R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 12-4413 EQEP_QPOSCNT Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	POSCNT	R/W	0h	This 32-bit Position Counter register counts up/down on every QEP pulse based on direction input. This counter acts as a position integrator whose count value is proportional to position from a give reference point.

4.4.5.2 EQEP_QPOSINIT Register (Offset = 4h) [reset = 0h]

EQEP_QPOSINIT is shown in Figure 12-2327 and described in Table 12-4415.

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Position Counter Initialization register

Table 12-4414 EQEP_QPOSINIT Instances

Instance	Physical Address
EQEP0_REG	2320 0004h
EQEP1_REG	2321 0004h
EQEP2_REG	2322 0004h

Figure 12-2327 EQEP_QPOSINIT Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
INITPOS
R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 12-4415 EQEP_QPOSINIT Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	INITPOS	R/W	0h	This register contains the position value to be used to initialize the Position Counter based on external strobe or Index event. Position Counter can be initialized through software.

4.4.5.3 EQEP_QPOSMAX Register (Offset = 8h) [reset = 0h]

EQEP_QPOSMAX is shown in Figure 12-2328 and described in Table 12-4417.

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Maximum Position Count register

Table 12-4416 EQEP_QPOSMAX Instances

Instance	Physical Address
EQEP0_REG	2320 0008h
EQEP1_REG	2321 0008h
EQEP2_REG	2322 0008h

Figure 12-2328 EQEP_QPOSMAX Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
MAXPOS
R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 12-4417 EQEP_QPOSMAX Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	MAXPOS	R/W	0h	This register contains the maximum Position Counter value for error checking in index reset mode or to reset the Position Counter based on the maximum count value.

4.4.5.4 EQEP_QPOSCMP Register (Offset = Ch) [reset = 0h]

EQEP_QPOSCMP is shown in Figure 12-2329 and described in Table 12-4419.

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Position Compare register

Table 12-4418 EQEP_QPOSCMP Instances

Instance	Physical Address
EQEP0_REG	2320 000Ch
EQEP1_REG	2321 000Ch
EQEP2_REG	2322 000Ch

Figure 12-2329 EQEP_QPOSCMP Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
POSCMP
R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 12-4419 EQEP_QPOSCMP Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	POSCMP	R/W	0h	Position compare value in this register is compared with the Position Counter (EQEP_QPOSCNT[31-0] POSCNT) to optionally generate interrupt on compare match.

4.4.5.5 EQEP_QPOSILAT Register (Offset = 10h) [reset = 0h]

EQEP_QPOSILAT is shown in Figure 12-2330 and described in Table 12-4421.

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Index Position Latch register

Table 12-4420 EQEP_QPOSILAT Instances

Instance	Physical Address
EQEP0_REG	2320 0010h
EQEP1_REG	2321 0010h
EQEP2_REG	2322 0010h

Figure 12-2330 EQEP_QPOSILAT Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
IPOSLAT
R-0h

LEGEND: R = Read Only; -n = value after reset

Table 12-4421 EQEP_QPOSILAT Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	IPOSLAT	R	0h	Position Counter value can be latched into this register on index event as defined by the EQEP_QDEC_QEP_CTL[21-20] IEL bit field.

4.4.5.6 EQEP_QPOSSLAT Register (Offset = 14h) [reset = 0h]

EQEP_QPOSSLAT is shown in Figure 12-2331 and described in Table 12-4423.

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Strobe Position Latch register

Table 12-4422 EQEP_QPOSSLAT Instances

Instance	Physical Address
EQEP0_REG	2320 0014h
EQEP1_REG	2321 0014h
EQEP2_REG	2322 0014h

Figure 12-2331 EQEP_QPOSSLAT Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SPOSLAT
R-0h

LEGEND: R = Read Only; -n = value after reset

Table 12-4423 EQEP_QPOSSLAT Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	SPOSLAT	R	0h	Position Counter value can be latched into this register on strobe event as defined by the EQEP_QDEC_QEP_CTL[22] SEL bit.

4.4.5.7 EQEP_QPOSLAT Register (Offset = 18h) [reset = 0h]

EQEP_QPOSLAT is shown in Figure 12-2332 and described in Table 12-4425.

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QEP Position Counter Latch register

Table 12-4424 EQEP_QPOSLAT Instances

Instance	Physical Address
EQEP0_REG	2320 0018h
EQEP1_REG	2321 0018h
EQEP2_REG	2322 0018h

Figure 12-2332 EQEP_QPOSLAT Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
POSLAT
R-0h

LEGEND: R = Read Only; -n = value after reset

Table 12-4425 EQEP_QPOSLAT Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	POSLAT	R	0h	Position Counter value can be latched into this register on unit time out event.

4.4.5.8 EQEP_QUTMR Register (Offset = 1Ch) [reset = 0h]

EQEP_QUTMR is shown in Figure 12-2333 and described in Table 12-4427.

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QEP Unit Timer register

Table 12-4426 EQEP_QUTMR Instances

Instance	Physical Address
EQEP0_REG	2320 001Ch
EQEP1_REG	2321 001Ch
EQEP2_REG	2322 001Ch

Figure 12-2333 EQEP_QUTMR Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
UNITTMR
R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 12-4427 EQEP_QUTMR Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	UNITTMR	R/W	0h	This register acts as time base for unit time event generation. When this timer value matches with unit time period value, unit time event is generated.

4.4.5.9 EQEP_QUPRD Register (Offset = 20h) [reset = 0h]

EQEP_QUPRD is shown in Figure 12-2334 and described in Table 12-4429.

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QEP Unit Period register

Table 12-4428 EQEP_QUPRD Instances

Instance	Physical Address
EQEP0_REG	2320 0020h
EQEP1_REG	2321 0020h
EQEP2_REG	2322 0020h

Figure 12-2334 EQEP_QUPRD Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
UNITPRD
R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 12-4429 EQEP_QUPRD Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	UNITPRD	R/W	0h	This register contains the period count for unit timer to generate periodic unit time events to latch the EQEP position information at periodic interval and optionally to generate interrupt.

4.4.5.10 EQEP_QWD_TMR_PRD Register (Offset = 24h) [reset = 0h]

EQEP_QWD_TMR_PRD is shown in Figure 12-2335 and described in Table 12-4431.

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QEP Watchdog Timer and Period register

Table 12-4430 EQEP_QWD_TMR_PRD Instances

Instance	Physical Address
EQEP0_REG	2320 0024h
EQEP1_REG	2321 0024h
EQEP2_REG	2322 0024h

Figure 12-2335 EQEP_QWD_TMR_PRD Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
QWDPRD																QWDTMR
R/W-0h																R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 12-4431 EQEP_QWD_TMR_PRD Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	QWDPRD	R/W	0h	This field contains the time-out count for the QEP peripheral watch dog timer. When watch dog timer value matches with the watch dog period value, status flag is set to indicate the stall.
15-0	QWDTMR	R/W	0h	This field acts as time base for watch dog to detect stalls. When this timer value matches with watch dog period value, watch dog timeout event is generated. This register is reset upon edge transition in Quadrature clock indicating the motion.

4.4.5.11 EQEP_QDEC_QEP_CTL Register (Offset = 28h) [reset = 0h]

EQEP_QDEC_QEP_CTL is shown in Figure 12-2336 and described in Table 12-4433.

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Quadrature Decoder and QEP Control register

Table 12-4432 EQEP_QDEC_QEP_CTL Instances

Instance	Physical Address
EQEP0_REG	2320 0028h
EQEP1_REG	2321 0028h
EQEP2_REG	2322 0028h

Figure 12-2336 EQEP_QDEC_QEP_CTL Register

31	30	29	28	27	26	25	24
FREE_SOFT		PCRM		SEI		IEI
R/W-0h		R/W-0h		R/W-0h		R/W-0h

23	22	21	20	19	18	17	16
SWI	SEL	IEL		QPEN	QCLM	UTE	WDE
R/W-0h	R/W-0h	R/W-0h		R/W-0h	R/W-0h	R/W-0h	R/W-0h

15	14	13	12	11	10	9	8
QSRC		SOEN	SPSEL	XCR	SWAP	IGATE	QAP
R/W-0h		R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h

7	6	5	4	3	2	1	0
QBP	QIP	QSP	RESERVED
R/W-0h	R/W-0h	R/W-0h	R-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 12-4433 EQEP_QDEC_QEP_CTL Register Field Descriptions

Bit	Field	Type	Reset	Description
31-30	FREE_SOFT	R/W	0h	POSCNT Behavior: 0h = Position Counter stops immediately on emulation suspend 1h = Position Counter continues to count until the rollover 1x = Position Counter is unaffected by emulation suspend QWDTMR Behavior: 2h = Watchdog Counter stops immediately 3h = Watchdog Counter counts until WD period match roll over 1x = Watchdog Counter is unaffected by emulation suspend UNITTMR Behavior: 2h = Unit Timer stops immediately 3h = Unit Timer counts until period rollover 1x = Unit Timer is unaffected by emulation suspend QCTMR Behavior: 0h = Capture Timer stops immediately 1h = Capture Timer counts until next unit period event 1x = Capture Timer is unaffected by emulation suspend
29-28	PCRM	R/W	0h	Position Counter Reset Mode: 0h = Index event resets the Position Counter for each revolution 1h = Maximum position event resets the Position Counter 2h = RESET ONCE: First Index event resets the Position Counter 3h = Unit Time event resets the Position Counter
27-26	SEI	R/W	0h	Strobe Event Initialization of Position Counter: 0h = Do nothing (action disabled) 2h = Initialize Position Counter on Rising edge of QEPS signal 3h = Clockwise Direction: Initialize Position Counter on Rising edge of QEPS strobe. Counter Clockwise Direction: Initialize Position Counter on Falling edge of QEPS strobe.
25-24	IEI	R/W	0h	Index Event Initialization of Position Counter: 0h = Do nothing (action disabled) 2h = Initialize Position Counter on Rising edge of index signal 3h = Initialize Position Counter on Falling edge of index signal
23	SWI	R/W	0h	Software Initialization of Position Counter: 0h = Do nothing (action disabled) 1h = Initialize Position Counter, this bit is cleared automatically
22	SEL	R/W	0h	Strobe Event Latch of Position Counter: 0h = Latch Position Counter on Rising edge of strobe signal 1h = Clockwise Direction: Position Counter is latched on Rising edge of QEPS strobe. Counter Clockwise Direction: Position Counter is latched on Falling edge of QEPS strobe.
21-20	IEL	R/W	0h	Index Event Latch of Position Counter (Software Index Marker): 0h = Reserved 1h = Latch Position Counter on Rising edge of index signal 2h = Latch Position Counter on Falling edge of index signal 3h = Software Index Marker Latch the Position Counter and Quadrature direction flag on index event marker. Position Counter is latched to the EQEP_QPOSILAT[31-0] IPOSLAT bit field and direction flag is latched in the EQEP_QEP_STS_CT[4] QDLF bit.
19	QPEN	R/W	0h	Quadrature Position Counter Enable/Software Reset: 0h = Software Reset Initialize the internal operating Flag/read-only registers to reset value. Following registers and register bit fields are reset and EQEP control registers retains the same value after software reset: EQEP_QPOSSLAT, EQEP_QC_PRD_TLAT[31-16] QCTMRLAT, EQEP_QCPRDLAT, EQEP_EQEP_QEP_STS_CT 1h = QEP Position Counter is enabled
18	QCLM	R/W	0h	EQEP Capture Latch Mode: 0h = Latch on Position Counter read by CPU Capture Timer and Capture Period values are latched into the EQEP_QC_PRD_TLAT and EQEP_QCPRDLAT registers when CPU reads the EQEP_QPOSCNT register. 1h = Latch on Unit Time Out. Position Counter, Capture Timer and Capture Period values are latched into the EQEP_QPOSLAT register, EQEP_QC_PRD_TLAT[31-16] QCTMRLAT bit field and EQEP_QCPRDLAT register on Unit Time out
17	UTE	R/W	0h	QEP Unit Timer Enable: 0h = Disable QEP Unit Timer 1h = Enable Unit Timer
16	WDE	R/W	0h	QEP Watchdog Enable: 0h = Disable QEP watchdog 1h = Enable QEP watchdog
15-14	QSRC	R/W	0h	Position Counter Source selection: 0h = Quadrature count mode (QCLK = iCLK, QDIR = iDIR) 1h = Direction count mode (QCLK = xCLK, QDIR = xDIR) 2h = UP count mode for frequency measurement (QCLK = xCLK, QDIR = 1) 3h = DOWN Count mode for frequency measurement (QCLK = xCLK, QDIR = 0)
13	SOEN	R/W	0h	Enable Position Compare Sync Output: 0h = Disable position-compare sync output 1h = Enable position compare sync output
12	SPSEL	R/W	0h	Sync Output Pin Selection: 0h = Index pin is used for sync output 1h = Strobe pin is used for sync output
11	XCR	R/W	0h	External Clock Rate: 0h = 2× resolution: Count the rising/Falling edge 1h = 1× resolution: Count the Rising edge only
10	SWAP	R/W	0h	CLK/DIR Signal Source for Position Counter: 0h = Quadrature clock inputs are not swapped 1h = Quadrature clock inputs are swapped
9	IGATE	R/W	0h	Index Pulse Gating Option: 0h = Disable gating of Index pulse 1h = Gate the index pin with strobe
8	QAP	R/W	0h	QEPA Input Polarity: 0h = No effect 1h = Negate QEPA input
7	QBP	R/W	0h	QEPB Input Polarity: 0h = No effect 1h = Negate QEPB input
6	QIP	R/W	0h	QEPI Input Polarity: 0h = No effect 1h = Negate QEPI input
5	QSP	R/W	0h	QEPS Input Polarity: 0h = No effect 1h = Negate QEPS input
4-0	RESERVED	R	0h	Reserved

4.4.5.12 EQEP_QCAP_QPOS_CTL Register (Offset = 2Ch) [reset = 0h]

EQEP_QCAP_QPOS_CTL is shown in Figure 12-2337 and described in Table 12-4435.

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QEP Capture and Position Compare Control register

Table 12-4434 EQEP_QCAP_QPOS_CTL Instances

Instance	Physical Address
EQEP0_REG	2320 002Ch
EQEP1_REG	2321 002Ch
EQEP2_REG	2322 002Ch

Figure 12-2337 EQEP_QCAP_QPOS_CTL Register

31	30	29	28	27	26	25	24
PCSHDW	PCLOAD	PCPOL	PCE	PCSPW
R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h

23	22	21	20	19	18	17	16
PCSPW
R/W-0h

15	14	13	12	11	10	9	8
CEN	RESERVED
R/W-0h	R-0h

7	6	5	4	3	2	1	0
RESERVED	CCPS			UPPS
R-0h	R/W-0h			R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 12-4435 EQEP_QCAP_QPOS_CTL Register Field Descriptions

Bit	Field	Type	Reset	Description
31	PCSHDW	R/W	0h	Position-Compare Shadow Enable: 0h = Shadow disabled, load Immediate 1h = Shadow enabled
30	PCLOAD	R/W	0h	Position Compare Shadow Load Mode: 0h = Load On POSCNT = 0 1h = Load When POSCNT = POSCMP
29	PCPOL	R/W	0h	Polarity of Sync Output: 0h = Active HIGH pulse output 1h = Active LOW pulse output
28	PCE	R/W	0h	Position Compare Enable/Disable: 0h = Disable Mode (no inter or pulse) 1h = Enable Mode
27-16	PCSPW	R/W	0h	Select Pulse Width Period in EQEP_FICLK Cycles: 0h = 1 × 4 × EQEP_FICLK cycles 1h = 2 × 4 × EQEP_FICLK cycles ... FFFh = 4096 × 4 × EQEP_FICLK cycles
15	CEN	R/W	0h	Enable EQEP Capture: 0h = EQEP Capture unit is disabled 1h = EQEP Capture unit is enabled
14-7	RESERVED	R	0h	Reserved
6-4	CCPS	R/W	0h	EQEP Capture Timer Clock Prescalar: 0h = CAPCLK = EQEP_FICLK/1 1h = CAPCLK = EQEP_FICLK/2 2h = CAPCLK = EQEP_FICLK/4 3h = CAPCLK = EQEP_FICLK/8 4h = CAPCLK = EQEP_FICLK/16 5h = CAPCLK = EQEP_FICLK/32 6h = CAPCLK = EQEP_FICLK/64 7h = CAPCLK = EQEP_FICLK/128
3-0	UPPS	R/W	0h	Unit Position Event Prescalar: 0h = UPEVNT = QCLK/1 1h = UPEVNT = QCLK/2 2h = UPEVNT = QCLK/4 3h = UPEVNT = QCLK/8 4h = UPEVNT = QCLK/16 5h = UPEVNT = QCLK/32 6h = UPEVNT = QCLK/64 7h = UPEVNT = QCLK/128 8h = UPEVNT = QCLK/256 9h = UPEVNT = QCLK/512 Ah = UPEVNT = QCLK/1024 Bh = UPEVNT = QCLK/2048 Ch = Reserved Dh = Reserved Eh = Reserved Fh = Reserved

4.4.5.13 EQEP_QINT_EN_FLG Register (Offset = 30h) [reset = 0h]

EQEP_QINT_EN_FLG is shown in Figure 12-2338 and described in Table 12-4437.

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QEP Interrupt Control and Flag register

Table 12-4436 EQEP_QINT_EN_FLG Instances

Instance	Physical Address
EQEP0_REG	2320 0030h
EQEP1_REG	2321 0030h
EQEP2_REG	2322 0030h

Figure 12-2338 EQEP_QINT_EN_FLG Register

31	30	29	28	27	26	25	24
RESERVED				UTOI_FLG	IELI_FLG	SELI_FLG	PCMI_FLG
R-0h				R-0h	R-0h	R-0h	R-0h

23	22	21	20	19	18	17	16
PCRI_FLG	PCOI_FLG	PCUI_FLG	WTOI_FLG	QDCI_FLG	QPEI_FLG	PCEI_FLG	INT_FLG
R-0h	R-0h	R-0h	R-0h	R-0h	R-0h	R-0h	R-0h

15	14	13	12	11	10	9	8
RESERVED				UTOI_EN	IELI_EN	SELI_EN	PCMI_EN
R-0h				R/W-0h	R/W-0h	R/W-0h	R/W-0h

7	6	5	4	3	2	1	0
PCRI_EN	PCOI_EN	PCUI_EN	WTOI_EN	QDCI_EN	QPEI_EN	PCEI_EN	RESERVED
R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h	R-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 12-4437 EQEP_QINT_EN_FLG Register Field Descriptions

Bit	Field	Type	Reset	Description
31-28	RESERVED	R	0h	Reserved
27	UTOI_FLG	R	0h	Unit Time Out Interrupt Flag: Read 0h = Indicates no interrupt is generated 1h = Set by EQEP unit timer period match
26	IELI_FLG	R	0h	Index Event Latch Interrupt Flag: Read 0h = Indicates no interrupt is generated 1h = This bit is set after latching the EQEP_QPOSCNT[31-0] POSCNT bit filed to EQEP_QPOSILAT[31-0] IPOSLAT bit filed
25	SELI_FLG	R	0h	Strobe Event Latch Interrupt Flag: Read 0h = Indicates no interrupt is generated 1h = This bit is set after latching the EQEP_QPOSCNT[31-0] POSCNT bit filed to EQEP_QPOSSLAT[31-0] SPOSLAT bit filed
24	PCMI_FLG	R	0h	EQEP Compare Match Event Interrupt Flag: Read 0h = Indicates no interrupt is generated 1h = This bit is set on position compare match
23	PCRI_FLG	R	0h	Position Compare Ready Interrupt Flag: Read 0h = Indicates no interrupt is generated 1h = This bit is set on position compare FIFO level match
22	PCOI_FLG	R	0h	Position Counter Overflow Interrupt Flag: Read 0h = Indicates no interrupt is generated 1h = This bit is set during the EQEP_QPOSCNT[31-0] POSCNT bit filed overflow
21	PCUI_FLG	R	0h	Position Counter Underflow Interrupt Flag: Read 0h = Indicates no interrupt is generated 1h = This bit is set during the EQEP_QPOSCNT[31-0] POSCNT bit field underflow
20	WTOI_FLG	R	0h	Watchdog Timeout Interrupt Flag: Read 0h = Indicates no interrupt is generated 1h = Set by watch dog (monitoring QEPA & QEPB) timeout
19	QDCI_FLG	R	0h	Quadrature Direction Change Interrupt Flag: Read 0h = Indicates no interrupt is generated 1h = This bit is set during change of direction
18	QPEI_FLG	R	0h	Quadrature Phase Error Interrupt Flag: Read 0h = Indicates no interrupt is generated 1h = Set on simultaneous transition of QEPA & QEPB
17	PCEI_FLG	R	0h	Position Counter Error Interrupt Flag: Read 0h = Indicates no interrupt is generated 1h = This is set during error in position count between index
16	INT_FLG	R	0h	Global Interrupt Status Flag: Read 0h = Indicates no interrupt is generated Read 1h on this bit indicates that an interrupt was generated from one of the following events.
15-12	RESERVED	R	0h	Reserved
11	UTOI_EN	R/W	0h	Unit Time Out Interrupt Enable: 0h = Interrupt is disabled 1h = Interrupt is enabled
10	IELI_EN	R/W	0h	Index Event Latch Interrupt Enable: 0h = Interrupt is disabled 1h = Interrupt is enabled
9	SELI_EN	R/W	0h	Strobe Event Latch Interrupt Enable: 0h = Interrupt is disabled 1h = Interrupt is enabled
8	PCMI_EN	R/W	0h	Position Compare Match Interrupt Enable: 0h = Interrupt is disabled 1h = Interrupt is enabled
7	PCRI_EN	R/W	0h	Position Compare Ready Interrupt Enable: 0h = Interrupt is disabled 1h = Interrupt is enabled
6	PCOI_EN	R/W	0h	Position Counter Overflow Interrupt Enable: 0h = Interrupt is disabled 1h = Interrupt is enabled
5	PCUI_EN	R/W	0h	Position Counter Underflow Interrupt Enable: 0h = Interrupt is disabled 1h = Interrupt is enabled
4	WTOI_EN	R/W	0h	Watchdog Time Out Interrupt Enable: 0h = Interrupt is disabled 1h = Interrupt is enabled
3	QDCI_EN	R/W	0h	Quadrature Direction Change Interrupt Enable: 0h = Interrupt is disabled 1h = Interrupt is enabled
2	QPEI_EN	R/W	0h	Quadrature Phase Error Interrupt Enable: 0h = Interrupt is disabled 1h = Interrupt is enabled
1	PCEI_EN	R/W	0h	Position Counter Error Interrupt Enable: 0h = Interrupt is disabled 1h = Interrupt is enabled
0	RESERVED	R	0h	Reserved

4.4.5.14 EQEP_QINT_CLR_FRC Register (Offset = 34h) [reset = 0h]

EQEP_QINT_CLR_FRC is shown in Figure 12-2339 and described in Table 12-4439.

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QEP Interrupt Clear and Forcing register

Table 12-4438 EQEP_QINT_CLR_FRC Instances

Instance	Physical Address
EQEP0_REG	2320 0034h
EQEP1_REG	2321 0034h
EQEP2_REG	2322 0034h

Figure 12-2339 EQEP_QINT_CLR_FRC Register

31	30	29	28	27	26	25	24
RESERVED				UTOI_FRC	IELI_FRC	SELI_FRC	PCMI_FRC
R-0h				W1S-0h	W1S-0h	W1S-0h	W1S-0h

23	22	21	20	19	18	17	16
PCRI_FRC	PCOI_FRC	PCUI_FRC	WTOI_FRC	QDCI_FRC	QPEI_FRC	PCEI_FRC	RESERVED
W1S-0h	W1S-0h	W1S-0h	W1S-0h	W1S-0h	W1S-0h	W1S-0h	R-0h

15	14	13	12	11	10	9	8
RESERVED				UTOI_CLR	IELI_CLR	SELI_CLR	PCMI_CLR
R-0h				W1C-0h	W1C-0h	W1C-0h	W1C-0h

7	6	5	4	3	2	1	0
PCRI_CLR	PCOI_CLR	PCUI_CLR	WTOI_CLR	QDCI_CLR	QPEI_CLR	PCEI_CLR	INT_CLR
W1C-0h	W1C-0h	W1C-0h	W1C-0h	W1C-0h	W1C-0h	W1C-0h	W1C-0h

LEGEND: W = Write Only; W1C = Write 1 to Clear Bit; W1S = Write 1 to Set Bit; -n = value after reset

Table 12-4439 EQEP_QINT_CLR_FRC Register Field Descriptions

Bit	Field	Type	Reset	Description
31-28	RESERVED	R	0h	Reserved
27	UTOI_FRC	W1S	0h	Unit Time Out Interrupt Force: 0h = No effect 1h = Force the interrupt
26	IELI_FRC	W1S	0h	Index Event Latch Interrupt Force: 0h = No effect 1h = Force the interrupt
25	SELI_FRC	W1S	0h	Strobe Event Latch Interrupt Force: 0h = No effect 1h = Force the interrupt
24	PCMI_FRC	W1S	0h	Position Compare Match Interrupt Force: 0h = No effect 1h = Force the interrupt
23	PCRI_FRC	W1S	0h	Position Compare Ready Interrupt Force: 0h = No effect 1h = Force the interrupt
22	PCOI_FRC	W1S	0h	Position Counter Overflow Interrupt Force: 0h = No effect 1h = Force the interrupt
21	PCUI_FRC	W1S	0h	Position Counter Underflow Interrupt Force: 0h = No effect 1h = Force the interrupt
20	WTOI_FRC	W1S	0h	Watchdog Time Out Interrupt Force: 0h = No effect 1h = Force the interrupt
19	QDCI_FRC	W1S	0h	Quadrature Direction Change Interrupt Force: 0h = No effect 1h = Force the interrupt
18	QPEI_FRC	W1S	0h	Quadrature Phase Error Interrupt Force: 0h = No effect 1h = Force the interrupt
17	PCEI_FRC	W1S	0h	Position Counter Error Interrupt Force: 0h = No effect 1h = Force the interrupt
16-12	RESERVED	R	0h	Reserved
11	UTOI_CLR	W1C	0h	Clear Unit Time Out Interrupt Flag: Write 1h = Clears the interrupt flag
10	IELI_CLR	W1C	0h	Clear Index Event Latch Interrupt Flag: Write 1h = Clears the interrupt flag
9	SELI_CLR	W1C	0h	Clear Strobe Event Latch Interrupt Flag: Write 1h = Clears the interrupt flag
8	PCMI_CLR	W1C	0h	Clear QEP Compare Match Event Interrupt Flag: Write 1h = Clears the interrupt flag
7	PCRI_CLR	W1C	0h	Clear Position Compare Ready Interrupt Flag: Write 1h = Clears the interrupt flag
6	PCOI_CLR	W1C	0h	Clear Position Counter Overflow Interrupt Flag: Write 1h = Clears the interrupt flag
5	PCUI_CLR	W1C	0h	Clear Position Counter Underflow Interrupt Flag: Write 1h = Clears the interrupt flag
4	WTOI_CLR	W1C	0h	Clear Watchdog Timeout Interrupt Flag: Write 1h = Clears the interrupt flag
3	QDCI_CLR	W1C	0h	Clear Quadrature Direction Change Interrupt Flag: Write 1h = Clears the interrupt flag
2	QPEI_CLR	W1C	0h	Clear Quadrature Phase Error Interrupt Flag: Write 1h = Clears the interrupt flag
1	PCEI_CLR	W1C	0h	Clear Position Counter Error Interrupt Flag: Write 1h = Clears the interrupt flag
0	INT_CLR	W1C	0h	Global Interrupt Clear Flag: Write 1h = Clear the interrupt flag and enable further interrupts to be generated if any of the event flags are set to 1h.

4.4.5.15 EQEP_QEP_STS_CT Register (Offset = 38h) [reset = 0h]

EQEP_QEP_STS_CT is shown in Figure 12-2340 and described in Table 12-4441.

Return to Summary Table.

QEP Status and Capture Timer register

Table 12-4440 EQEP_QEP_STS_CT Instances

Instance	Physical Address
EQEP0_REG	2320 0038h
EQEP1_REG	2321 0038h
EQEP2_REG	2322 0038h

Figure 12-2340 EQEP_QEP_STS_CT Register

31	30	29	28	27	26	25	24
QCTMR
R/W-0h

23	22	21	20	19	18	17	16
QCTMR
R/W-0h

15	14	13	12	11	10	9	8
RESERVED
R-0h

7	6	5	4	3	2	1	0
RESERVED	FIDF	QDF	QDLF	COEF	CDEF	FIMF	PCEF
R-0h	R-0h	R-0h	R-0h	R/W1C-0h	R/W1C-0h	R/W1C-0h	R-0h

LEGEND: R = Read Only; R/W = Read/Write; R/W1C = Read/Write 1 to Clear Bit; -n = value after reset

Table 12-4441 EQEP_QEP_STS_CT Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	QCTMR	R/W	0h	This field provides time base for edge capture unit.
15-7	RESERVED	R	0h	Reserved
6	FIDF	R	0h	Direction on First Index Marker Status of the direction is latched on first index event marker.
5	QDF	R	0h	Quadrature Direction Flag 0h = Anti-clockwise rotation or reverse movement 1h = Clockwise rotation or forward movement
4	QDLF	R	0h	EQEP Direction Latch Flag Status of direction is latched on every index event marker.
3	COEF	R/W1C	0h	Capture Overflow Error Flag 0h = Sticky bit, cleared by writing 1h 1h = Overflow occurred in EQEP Capture Timer (QEPCTMR)
2	CDEF	R/W1C	0h	Capture Direction Error Flag 0h = Sticky bit, cleared by writing 1h 1h = Direction change occurred between the capture position event
1	FIMF	R/W1C	0h	First Index Marker Flag 0h = Sticky bit, cleared by writing 1h 1h = Set by first occurrence of index pulse
0	PCEF	R	0h	Position Counter Error Flag This bit is not sticky bit and it is updated for every index event. 0h = No error occurred during the last index transition 1h = Position Counter error

4.4.5.16 EQEP_QC_PRD_TLAT Register (Offset = 3Ch) [reset = 0h]

EQEP_QC_PRD_TLAT is shown in Figure 12-2341 and described in Table 12-4443.

Return to Summary Table.

QEP Capture Period and Timer Latch register

Table 12-4442 EQEP_QC_PRD_TLAT Instances

Instance	Physical Address
EQEP0_REG	2320 003Ch
EQEP1_REG	2321 003Ch
EQEP2_REG	2322 003Ch

Figure 12-2341 EQEP_QC_PRD_TLAT Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
QCTMRLAT																QCPRD
R-0h																R/W-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 12-4443 EQEP_QC_PRD_TLAT Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	QCTMRLAT	R	0h	EQEP Capture Timer value can be latched into this register on two events: 1) Unit Timeout event 2) Reading the EQEP Position Counter
15-0	QCPRD	R/W	0h	This field holds the period count value between the last successive EQEP position events.

4.4.5.17 EQEP_QCPRDLAT Register (Offset = 40h) [reset = 0h]

EQEP_QCPRDLAT is shown in Figure 12-2342 and described in Table 12-4445.

Return to Summary Table.

QEP Capture Period Latch register

Table 12-4444 EQEP_QCPRDLAT Instances

Instance	Physical Address
EQEP0_REG	2320 0040h
EQEP1_REG	2321 0040h
EQEP2_REG	2322 0040h

Figure 12-2342 EQEP_QCPRDLAT Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED																QCPRDLAT
R-0h																R-0h

LEGEND: R = Read Only; -n = value after reset

Table 12-4445 EQEP_QCPRDLAT Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	RESERVED	R	0h	Reserved
15-0	QCPRDLAT	R	0h	EQEP capture period value can be latched into this register on two events: 1) Unit Timeout event 2) Reading the EQEP Position Counter

4.4.5.18 EQEP_PID Register (Offset = 5Ch) [reset = 44D31903h]

EQEP_PID is shown in Figure 12-2343 and described in Table 12-4447.

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Peripheral ID register

Table 12-4446 EQEP_PID Instances

Instance	Physical Address
EQEP0_REG	2320 005Ch
EQEP1_REG	2321 005Ch
EQEP2_REG	2322 005Ch

Figure 12-2343 EQEP_PID Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
REVISION
44D31903h

LEGEND: R = Read Only; -n = value after reset

Table 12-4447 EQEP_PID Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	REVISION	R	44D31903h	TI Internal Data Identifies the revision of the peripheral.