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SPRUIM2H May 2020 – October 2023 AM2431 , AM2432 , AM2434 , AM6411 , AM6412 , AM6421 , AM6422 , AM6441 , AM6442

5.4.6.3 MCU_PLL0_CFG Registers

Table 5-1234 lists the memory-mapped registers for the MCU_PLL0_CFG. All register offset addresses not listed in Table 5-1234 should be considered as reserved locations and the register contents should not be modified.

Table 5-1233 MCU_PLL0_CFG Instances

Instance	Base Address
MCU_PLL0_CFG	0404 0000h

Table 5-1234 MCU_PLL0_CFG Registers

Offset	Acronym	Register Name	MCU_PLL0_CFG Physical Address
0h	MCU_PLL0_PID	Peripheral Identification Register	0404 0000h
8h	MCU_PLL0_CFG	PLL0 Configuration	0404 0008h
10h	MCU_PLL0_LOCKKEY0	PLL0 Lock Key 0 Register	0404 0010h
14h	MCU_PLL0_LOCKKEY1	PLL0 Lock Key 1 Register	0404 0014h
20h	MCU_PLL0_CTRL	PLL0 Control	0404 0020h
24h	MCU_PLL0_STAT	PLL0 Status	0404 0024h
30h	MCU_PLL0_FREQ_CTRL0	PLL0 Frequency Control 0 Register	0404 0030h
34h	MCU_PLL0_FREQ_CTRL1	PLL0 Frequency Control 1 Register	0404 0034h
38h	MCU_PLL0_DIV_CTRL	PLL0 Output Clock Divider Register	0404 0038h
40h	MCU_PLL0_SS_CTRL	PLL0 Spread Spectrum Modulator Control Register	0404 0040h
44h	MCU_PLL0_SS_SPREAD	PLL0 Spread Spectrum Modulator Frequency Control Register	0404 0044h
60h	MCU_PLL0_CAL_CTRL	PLL0 Calibration Control Register	0404 0060h
64h	MCU_PLL0_CAL_STAT	PLL0 Calibration Status Register	0404 0064h
80h	MCU_PLL0_HSDIV_CTRL0	PLL0 High Speed Divider Control 0 Register	0404 0080h
84h	MCU_PLL0_HSDIV_CTRL1	PLL0 High Speed Divider Control 1 Register	0404 0084h
88h	MCU_PLL0_HSDIV_CTRL2	PLL0 High Speed Divider Control 2 Register	0404 0088h
8Ch	MCU_PLL0_HSDIV_CTRL3	PLL0 High Speed Divider Control 3 Register	0404 008Ch
90h	MCU_PLL0_HSDIV_CTRL4	PLL0 High Speed Divider Control 4 Register	0404 0090h

4.6.3.1 MCU_PLL0_PID Register (Offset = 0h) [reset = 61820000h]

MCU_PLL0_PID is shown in Figure 5-616 and described in Table 5-1236.

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Peripheral release details.

Table 5-1235 MCU_PLL0_PID Instances

Instance	Physical Address
MCU_PLL0_CFG	0404 0000h

Figure 5-616 MCU_PLL0_PID Register

31	30	29	28	27	26	25	24
SCHEME		BU		FUNC
R-1h		R-2h		R-182h

23	22	21	20	19	18	17	16
FUNC
R-182h

15	14	13	12	11	10	9	8
R_RTL					X_MAJOR
R-0h					R-0h

7	6	5	4	3	2	1	0
CUSTOM		Y_MINOR
R-0h		R-0h

LEGEND: R = Read Only; -n = value after reset

Table 5-1236 MCU_PLL0_PID Register Field Descriptions

Bit	Field	Type	Reset	Description
31-30	SCHEME	R	1h	PID follows new scheme
29-28	BU	R	2h	Business unit - Processors
27-16	FUNC	R	182h	Module functional identifier - CTRL MMR
15-11	R_RTL	R	0h	RTL revision number - actual value determined by RTL
10-8	X_MAJOR	R	0h	Major revision number - actual value determined by RTL
7-6	CUSTOM	R	0h	Custom revision number - actual value determined by RTL
5-0	Y_MINOR	R	0h	Minor revision number - actual value determined by RTL

4.6.3.2 MCU_PLL0_CFG Register (Offset = 8h) [reset = 1F0801h]

MCU_PLL0_CFG is shown in Figure 5-617 and described in Table 5-1238.

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Indicates the configuration of this PLL.

Table 5-1237 MCU_PLL0_CFG Instances

Instance	Physical Address
MCU_PLL0_CFG	0404 0008h

Figure 5-617 MCU_PLL0_CFG Register

31	30	29	28	27	26	25	24
HSDIV_PRSNC
R-1Fh

23	22	21	20	19	18	17	16
HSDIV_PRSNC
R-1Fh

15	14	13	12	11	10	9	8
RESERVED			SSM_TYPE		RESERVED		SSM_WVTBL
R-0h			R-1h		R-0h		R-0h

7	6	5	4	3	2	1	0
RESERVED						PLL_TYPE
R-0h						R-1h

LEGEND: R = Read Only; -n = value after reset

Table 5-1238 MCU_PLL0_CFG Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	HSDIV_PRSNC	R	1Fh	High Speed Divider Presence Each bit Indicates the presence of High Speed dividers 0-15. By definition HSDIV[4:0] are connected the PLL FOUTVCO output clock and HSDIV[15:5] are connected to the PLL FOUTPOSTDIV output clock
15-13	RESERVED	R	0h	Reserved
12-11	SSM_TYPE	R	1h	Spread spectrum module presence 0h - SSM is not present 1h - SSM is present 2h - Reserved 3h - Reserved
10-9	RESERVED	R	0h	Reserved
8	SSM_WVTBL	R	0h	Spread spectrum wave table presence 0h - SSM Wave table is not present 1h - SSM Wave table is present
7-2	RESERVED	R	0h	Reserved
1-0	PLL_TYPE	R	1h	Indicates PLL type 0h - Fractional PLL 1h - FractionalF PLL 2h - De-Skew PLL

4.6.3.3 MCU_PLL0_LOCKKEY0 Register (Offset = 10h) [reset = 0h]

MCU_PLL0_LOCKKEY0 is shown in Figure 5-618 and described in Table 5-1240.

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Lower 32-bits of PLL0 register write lock key This register must be written with the designated key value followed by a write to PLL0_KICK1 with its key value before PLL0 registers can be written.

Table 5-1239 MCU_PLL0_LOCKKEY0 Instances

Instance	Physical Address
MCU_PLL0_CFG	0404 0010h

Figure 5-618 MCU_PLL0_LOCKKEY0 Register

31	30	29	28	27	26	25	24
KEY
R/W-0h

23	22	21	20	19	18	17	16
KEY
R/W-0h

15	14	13	12	11	10	9	8
KEY
R/W-0h

7	6	5	4	3	2	1	0
KEY							UNLOCKED
R/W-0h							R-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-1240 MCU_PLL0_LOCKKEY0 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-1	KEY	R/W	0h	Write the kick0 unlock value followed by the kick1 unlock value to unlock the write-protected Partition0 registers
0	UNLOCKED	R	0h	Unlock status. When set, indicates that the proper unlock sequence has been performed and the partition is unlocked for writing.

4.6.3.4 MCU_PLL0_LOCKKEY1 Register (Offset = 14h) [reset = 0h]

MCU_PLL0_LOCKKEY1 is shown in Figure 5-619 and described in Table 5-1242.

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Upper 32-bits of PLL0 register write lock key This register must be written with the designated key value following a write to PLL0_KICK0 with its key value before PLL0 registers can be written.

Table 5-1241 MCU_PLL0_LOCKKEY1 Instances

Instance	Physical Address
MCU_PLL0_CFG	0404 0014h

Figure 5-619 MCU_PLL0_LOCKKEY1 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
KEY
R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 5-1242 MCU_PLL0_LOCKKEY1 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	KEY	R/W	0h	Write the kick1 unlock value after the kick0 unlock value to unlock the write-protected Partition0 registers

4.6.3.5 MCU_PLL0_CTRL Register (Offset = 20h) [reset = 80010011h]

MCU_PLL0_CTRL is shown in Figure 5-620 and described in Table 5-1244.

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Controls PLL operation.

Table 5-1243 MCU_PLL0_CTRL Instances

Instance	Physical Address
MCU_PLL0_CFG	0404 0020h

Figure 5-620 MCU_PLL0_CTRL Register

31	30	29	28	27	26	25	24
BYPASS_EN	RESERVED
R/W-1h	R-0h

23	22	21	20	19	18	17	16
RESERVED							BYP_ON _LOCKLOSS
R-0h							R/W-1h

15	14	13	12	11	10	9	8
PLL_EN	RESERVED						INTL_BYP_EN
R/W-0h	R-0h						R/W-0h

7	6	5	4	3	2	1	0
RESERVED		CLK_4PH_EN	CLK_POSTDIV_EN	RESERVED		DSM_EN	DAC_EN
R-0h		R/W-0h	R/W-1h	R-0h		R/W-0h	R/W-1h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-1244 MCU_PLL0_CTRL Register Field Descriptions

Bit	Field	Type	Reset	Description
31	BYPASS_EN	R/W	1h	Bypass enable. This controls the glitch-free bypass mux. The bypass_en bit should be set prior to making any changes to the PLL settings. 0h - Synchronously select PLL and associated HSDIV clock outputs 1h - Synchronously select the reference clock for all PLL and HSDIV clock outputs
30-17	RESERVED	R	0h	Reserved
16	BYP_ON _LOCKLOSS	R/W	1h	Bypass on loss of PLL lock. This bit controls the PLL bypass mux to automatically switch the clock source to the reference clock when the PLL losses lock. 0h - Do not automatically switch to ref clock source on PLL lock loss 1h - Switch to ref clock source when PLL losses lock
15	PLL_EN	R/W	0h	PLL enable 0h - PLL is disabled 1h - PLL is enabled
14-9	RESERVED	R	0h	Reserved
8	INTL_BYP_EN	R/W	0h	PLL internal bypass enable. This is an asynchronous mux which can produce glitches on the output clocks during switching. 0h - Output clocks are derived from the VCO clock 1h - Output clocks are derived from the FREF reference clock
7-6	RESERVED	R	0h	Reserved
5	CLK_4PH_EN	R/W	0h	Enable 4-phase clock generator. This bit is ignored if clk_postdiv_en = 0 0h - 4-phase dividers disabled. FOUT1PHx and FOUTn clocks are held low. 1h - 4-phase dividers enabled. FOUT1PH0/90/180/270 and FOUT2, FOUT3, FOUT4 clocks are enabled.
4	CLK_POSTDIV_EN	R/W	1h	Post divide CLK enable 0h - Post divide powered down. FOUTPOSTDIV and all auxiliary PLL clocks (4-phase and synchronous divided clocks) are held low 1h - Post divide enabled. FOUTPOSTDIV, 4-phase and synchronous clocks are enabled.
3-2	RESERVED	R	0h	Reserved
1	DSM_EN	R/W	0h	Delta-Sigma modulator enable 0h - Delta-Sigma modulator is disabled (use integer divide mode) 1h - Delta-Sigma modulator is enabled (use fractional divide mode)
0	DAC_EN	R/W	1h	Enable fractional noise canceling DAC This bit has no function (DAC is always disabled) in integer divide mode (when dsm_en = 0) 0h - Fractional NC DAC is disabled (for Test modes only) 1h - Fractional NC DAC is enabled (ignored in integer divide mode)

4.6.3.6 MCU_PLL0_STAT Register (Offset = 24h) [reset = X]

MCU_PLL0_STAT is shown in Figure 5-621 and described in Table 5-1246.

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Indicates PLL status.

Table 5-1245 MCU_PLL0_STAT Instances

Instance	Physical Address
MCU_PLL0_CFG	0404 0024h

Figure 5-621 MCU_PLL0_STAT Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
RESERVED
R-0h

7	6	5	4	3	2	1	0
RESERVED							LOCK
R-0h							R-X

LEGEND: R = Read Only; -n = value after reset

Table 5-1246 MCU_PLL0_STAT Register Field Descriptions

Bit	Field	Type	Reset	Description
31-1	RESERVED	R	0h	Reserved
0	LOCK	R	X	PLL lock status. Software should wait for lock to be asserted before clearing the PLL_CTRL_bypass_en bit 0h - PLL is not locked 1h - PLL is locked

4.6.3.7 MCU_PLL0_FREQ_CTRL0 Register (Offset = 30h) [reset = 10h]

MCU_PLL0_FREQ_CTRL0 is shown in Figure 5-622 and described in Table 5-1248.

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PLL frequency programming values.

Table 5-1247 MCU_PLL0_FREQ_CTRL0 Instances

Instance	Physical Address
MCU_PLL0_CFG	0404 0030h

Figure 5-622 MCU_PLL0_FREQ_CTRL0 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED																				FB_DIV_INT
R-0h																				R/W-10h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-1248 MCU_PLL0_FREQ_CTRL0 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-12	RESERVED	R	0h	Reserved
11-0	FB_DIV_INT	R/W	10h	PLL feedback divider (integer portion) In Integer mode values of 16 - 3200 (decimal) are supported. In Fractional mode values of 20 to 320 are supported. 12'h010 - Divide by 16 12'h011 - Divide by 17 …. 12'h140 - Divide by 320 12'hC80 - Divide by 3200 12'hC81 - 12'hFFF - Not supported

4.6.3.8 MCU_PLL0_FREQ_CTRL1 Register (Offset = 34h) [reset = 0h]

MCU_PLL0_FREQ_CTRL1 is shown in Figure 5-623 and described in Table 5-1250.

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PLL frequency programming values.

Table 5-1249 MCU_PLL0_FREQ_CTRL1 Instances

Instance	Physical Address
MCU_PLL0_CFG	0404 0034h

Figure 5-623 MCU_PLL0_FREQ_CTRL1 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED								FB_DIV_FRAC
R-0h								R/W-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-1250 MCU_PLL0_FREQ_CTRL1 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-24	RESERVED	R	0h	Reserved
23-0	FB_DIV_FRAC	R/W	0h	PLL feedback divider (fractional portion) Supports values of 0 to 0.999999940395. The total feedback divide value is (fb_div_int + fb_div_frac / (2^24)) 24'h000000 - 0 24'h000001 - .000000059605 (1/(2^24)) 24'h000002 - .000000119209 (2/(2^24)) …. 24'h800000 - .500000000000 24'hFFFFFF - .999999940395 (1677215/(2^24))

4.6.3.9 MCU_PLL0_DIV_CTRL Register (Offset = 38h) [reset = 1020001h]

MCU_PLL0_DIV_CTRL is shown in Figure 5-624 and described in Table 5-1252.

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Divider values for the PLL output clocks.

Table 5-1251 MCU_PLL0_DIV_CTRL Instances

Instance	Physical Address
MCU_PLL0_CFG	0404 0038h

Figure 5-624 MCU_PLL0_DIV_CTRL Register

31	30	29	28	27	26	25	24
RESERVED					POST_DIV2
R-0h					R/W-1h

23	22	21	20	19	18	17	16
RESERVED					POST_DIV1
R-0h					R/W-2h

15	14	13	12	11	10	9	8
RESERVED
R-0h

7	6	5	4	3	2	1	0
RESERVED		REF_DIV
R-0h		R/W-1h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-1252 MCU_PLL0_DIV_CTRL Register Field Descriptions

Bit	Field	Type	Reset	Description
31-27	RESERVED	R	0h	Reserved
26-24	POST_DIV2	R/W	1h	Secondary post divider. Supports values of 1-7
23-19	RESERVED	R	0h	Reserved
18-16	POST_DIV1	R/W	2h	Primary post divider. To ensure correct operation, post_div1 must always be programmed to a value equal to or greater that post_div2. Supports values of 1-7 0h - Reserved (do not use) 1h - Divide by 1 2h - Divide by 2 3h - Divide by 3 4h - Divide by 4 5h - Divide by 5 6h - Divide by 6 7h - Divide by 7
15-6	RESERVED	R	0h	Reserved
5-0	REF_DIV	R/W	1h	Reference clock pre-divider. Supports values of 1-63 0h - Reserved (do not use) 1h - Divide by 1 2h - Divide by 2 3Fh - Divide by 63

4.6.3.10 MCU_PLL0_SS_CTRL Register (Offset = 40h) [reset = 80000000h]

MCU_PLL0_SS_CTRL is shown in Figure 5-625 and described in Table 5-1254.

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Controls the operation of the spread spectrum modulator.

Table 5-1253 MCU_PLL0_SS_CTRL Instances

Instance	Physical Address
MCU_PLL0_CFG	0404 0040h

Figure 5-625 MCU_PLL0_SS_CTRL Register

31	30	29	28	27	26	25	24
BYPASS_EN	RESERVED					WV_TBL_MAXADDR
R/W-1h	R-0h					R/W-0h

23	22	21	20	19	18	17	16
WV_TBL_MAXADDR						RESERVED
R/W-0h						R-0h

15	14	13	12	11	10	9	8
RESET	RESERVED
R/W-0h	R-0h

7	6	5	4	3	2	1	0
RESERVED			DOWNSPREAD_EN	RESERVED			WAVE_SEL
R-0h			R/W-0h	R-0h			R/W-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-1254 MCU_PLL0_SS_CTRL Register Field Descriptions

Bit	Field	Type	Reset	Description
31	BYPASS_EN	R/W	1h	Bypass the SS modulator. 0h - Spread spectrum modulation is enabled 1h - SSMOD is bypassed. No modulation of PLL frequency
30-26	RESERVED	R	0h	Reserved
25-18	WV_TBL_MAXADDR	R/W	0h	Wave table max address. Indicates the maximum number of address bits used to access the external wave table. These bits are not used if PLL_CFG_ssm_wvtbl = 0
17-16	RESERVED	R	0h	Reserved
15	RESET	R/W	0h	SSM reset. When set to 1 the SSM modulator is in reset
14-5	RESERVED	R	0h	Reserved
4	DOWNSPREAD_EN	R/W	0h	Selects center spread or down spread clock variance 0h - Center spread 1h - Down spread
3-1	RESERVED	R	0h	Reserved
0	WAVE_SEL	R/W	0h	Wave pattern select External wave table should only be selected if PLL_CFG_ssm_wvtbl = 1 0h - Use 128 point triangle wave table 1h - Use external wave table

4.6.3.11 MCU_PLL0_SS_SPREAD Register (Offset = 44h) [reset = 10001h]

MCU_PLL0_SS_SPREAD is shown in Figure 5-626 and described in Table 5-1256.

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Defines the spread spectrum modulation frequency.

Table 5-1255 MCU_PLL0_SS_SPREAD Instances

Instance	Physical Address
MCU_PLL0_CFG	0404 0044h

Figure 5-626 MCU_PLL0_SS_SPREAD Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED				MOD_DIV
R-0h				R/W-1h

15	14	13	12	11	10	9	8
RESERVED
R-0h

7	6	5	4	3	2	1	0
RESERVED			SPREAD
R-0h			R/W-1h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-1256 MCU_PLL0_SS_SPREAD Register Field Descriptions

Bit	Field	Type	Reset	Description
31-20	RESERVED	R	0h	Reserved
19-16	MOD_DIV	R/W	1h	Input clock divider. This divider sets the modulation frequency. Supports divide values of 1-63
15-5	RESERVED	R	0h	Reserved
4-0	SPREAD	R/W	1h	Sets the spread modulation depth. The depth is spread*0.1% 0h - Reserved (don't use) 1h - 0.1% 2h - 0.2% …. 10h - 1.6% 1Fh - 3.1%

4.6.3.12 MCU_PLL0_CAL_CTRL Register (Offset = 60h) [reset = 20000h]

MCU_PLL0_CAL_CTRL is shown in Figure 5-627 and described in Table 5-1258.

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Controls calibration of the Fractional F PLL.

Table 5-1257 MCU_PLL0_CAL_CTRL Instances

Instance	Physical Address
MCU_PLL0_CFG	0404 0060h

Figure 5-627 MCU_PLL0_CAL_CTRL Register

31	30	29	28	27	26	25	24
CAL_EN	RESERVED
R/W-0h	R-0h

23	22	21	20	19	18	17	16
RESERVED			FAST_CAL	RESERVED	CAL_CNT
R-0h			R/W-0h	R-0h	R/W-2h

15	14	13	12	11	10	9	8
CAL_BYP	RESERVED			CAL_IN
R/W-0h	R-0h			R/W-0h

7	6	5	4	3	2	1	0
CAL_IN
R/W-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-1258 MCU_PLL0_CAL_CTRL Register Field Descriptions

Bit	Field	Type	Reset	Description
31	CAL_EN	R/W	0h	Calibration enable to actively adjust for input skew 0h - Disabled. Static phase offset determined by analog matching only 1h - Enabled. Static phase offset adjusted by phase sensing at input
30-21	RESERVED	R	0h	Reserved
20	FAST_CAL	R/W	0h	Fast calibration enabled 0h - Normal operation 1h - Used for initial calibration if initial value is not already known
19	RESERVED	R	0h	Reserved
18-16	CAL_CNT	R/W	2h	Calibration loop programmable counter. Selects the number of PFD edges to wait after each calibration step defined by 2**cal_cnt
15	CAL_BYP	R/W	0h	Calibration bypass 0h - Use the calibration output to set the phase correction 1h - Use the cal_in input value to set the phase correction
14-12	RESERVED	R	0h	Reserved
11-0	CAL_IN	R/W	0h	Calibration input When cal_byp is 1'b0, this represents the initial condition for calibration. When cal_byp is 1'b1, this is the override value for calibration. Value is a signed integer with positive values delaying the faster path reset and negative values delaying the slower path reset.

4.6.3.13 MCU_PLL0_CAL_STAT Register (Offset = 64h) [reset = X]

MCU_PLL0_CAL_STAT is shown in Figure 5-628 and described in Table 5-1260.

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Indicates Fractional F PLL calibration status.

Table 5-1259 MCU_PLL0_CAL_STAT Instances

Instance	Physical Address
MCU_PLL0_CFG	0404 0064h

Figure 5-628 MCU_PLL0_CAL_STAT Register

31	30	29	28	27	26	25	24
CAL_LOCK	RESERVED
R-X	R-0h

23	22	21	20	19	18	17	16
RESERVED				LOCK_CNT
R-0h				R-X

15	14	13	12	11	10	9	8
RESERVED				CAL_OUT
R-0h				R-X

7	6	5	4	3	2	1	0
CAL_OUT
R-X

LEGEND: R = Read Only; -n = value after reset

Table 5-1260 MCU_PLL0_CAL_STAT Register Field Descriptions

Bit	Field	Type	Reset	Description
31	CAL_LOCK	R	X	Reserved for future use
30-20	RESERVED	R	0h	Reserved
19-16	LOCK_CNT	R	X	Reserved for future use
15-12	RESERVED	R	0h	Reserved
11-0	CAL_OUT	R	X	Output of the calibration block if cal_byp = 1'b0. If cal_byp = 1'b1 it is a buffer version of cal_in[11:0]. Can be used to read the phase calibration state to for later use as an override value to bypass skew calibration.

4.6.3.14 MCU_PLL0_HSDIV_CTRL0 Register (Offset = 80h) [reset = 0h]

MCU_PLL0_HSDIV_CTRL0 is shown in Figure 5-629 and described in Table 5-1262.

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Controls the PLL0 HSDIVIDER0 features and mode of operation.

Table 5-1261 MCU_PLL0_HSDIV_CTRL0 Instances

Instance	Physical Address
MCU_PLL0_CFG	0404 0080h

Figure 5-629 MCU_PLL0_HSDIV_CTRL0 Register

31	30	29	28	27	26	25	24
RESET	RESERVED
R/W-0h	R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
CLKOUT_EN	RESERVED						SYNC_DIS
R/W-0h	R-0h						R/W-0h

7	6	5	4	3	2	1	0
RESERVED	HSDIV
R-0h	R/W-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-1262 MCU_PLL0_HSDIV_CTRL0 Register Field Descriptions

Bit	Field	Type	Reset	Description
31	RESET	R/W	0h	Asynchronous divider reset When set to 1'b1, Internal counters are reset and output clock = 1'b0
30-16	RESERVED	R	0h	Reserved
15	CLKOUT_EN	R/W	0h	CLKOUT0 enable 0h - Synchronously disable CLKOUT0 1h - Synchronously enable CLKOUT0
14-9	RESERVED	R	0h	Reserved
8	SYNC_DIS	R/W	0h	Disable divider synchronization logic 0h - Changes to DIV value synchronized to prevent glitches 1h - Changes are asynchronous
7	RESERVED	R	0h	Reserved
6-0	HSDIV	R/W	0h	CLKOUT0 divider value (HSDIV1+1) Allowed values are 0-127

4.6.3.15 MCU_PLL0_HSDIV_CTRL1 Register (Offset = 84h) [reset = 0h]

MCU_PLL0_HSDIV_CTRL1 is shown in Figure 5-630 and described in Table 5-1264.

Return to Summary Table.

Controls the PLL0 HSDIVIDER1 features and mode of operation.

Table 5-1263 MCU_PLL0_HSDIV_CTRL1 Instances

Instance	Physical Address
MCU_PLL0_CFG	0404 0084h

Figure 5-630 MCU_PLL0_HSDIV_CTRL1 Register

31	30	29	28	27	26	25	24
RESET	RESERVED
R/W-0h	R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
CLKOUT_EN	RESERVED						SYNC_DIS
R/W-0h	R-0h						R/W-0h

7	6	5	4	3	2	1	0
RESERVED	HSDIV
R-0h	R/W-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-1264 MCU_PLL0_HSDIV_CTRL1 Register Field Descriptions

Bit	Field	Type	Reset	Description
31	RESET	R/W	0h	Asynchronous divider reset When set to 1'b1, Internal counters are reset and output clock = 1'b0
30-16	RESERVED	R	0h	Reserved
15	CLKOUT_EN	R/W	0h	CLKOUT0 enable 0h - Synchronously disable CLKOUT0 1h - Synchronously enable CLKOUT0
14-9	RESERVED	R	0h	Reserved
8	SYNC_DIS	R/W	0h	Disable divider synchronization logic 0h - Changes to DIV value synchronized to prevent glitches 1h - Changes are asynchronous
7	RESERVED	R	0h	Reserved
6-0	HSDIV	R/W	0h	CLKOUT0 divider value (HSDIV1+1) Allowed values are 0-127

4.6.3.16 MCU_PLL0_HSDIV_CTRL2 Register (Offset = 88h) [reset = 0h]

MCU_PLL0_HSDIV_CTRL2 is shown in Figure 5-631 and described in Table 5-1266.

Return to Summary Table.

Controls the PLL0 HSDIVIDER2 features and mode of operation.

Table 5-1265 MCU_PLL0_HSDIV_CTRL2 Instances

Instance	Physical Address
MCU_PLL0_CFG	0404 0088h

Figure 5-631 MCU_PLL0_HSDIV_CTRL2 Register

31	30	29	28	27	26	25	24
RESET	RESERVED
R/W-0h	R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
CLKOUT_EN	RESERVED						SYNC_DIS
R/W-0h	R-0h						R/W-0h

7	6	5	4	3	2	1	0
RESERVED	HSDIV
R-0h	R/W-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-1266 MCU_PLL0_HSDIV_CTRL2 Register Field Descriptions

Bit	Field	Type	Reset	Description
31	RESET	R/W	0h	Asynchronous divider reset When set to 1'b1, Internal counters are reset and output clock = 1'b0
30-16	RESERVED	R	0h	Reserved
15	CLKOUT_EN	R/W	0h	CLKOUT0 enable 0h - Synchronously disable CLKOUT0 1h - Synchronously enable CLKOUT0
14-9	RESERVED	R	0h	Reserved
8	SYNC_DIS	R/W	0h	Disable divider synchronization logic 0h - Changes to DIV value synchronized to prevent glitches 1h - Changes are asynchronous
7	RESERVED	R	0h	Reserved
6-0	HSDIV	R/W	0h	CLKOUT0 divider value (HSDIV1+1) Allowed values are 0-127

4.6.3.17 MCU_PLL0_HSDIV_CTRL3 Register (Offset = 8Ch) [reset = 0h]

MCU_PLL0_HSDIV_CTRL3 is shown in Figure 5-632 and described in Table 5-1268.

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Controls the PLL0 HSDIVIDER3 features and mode of operation.

Table 5-1267 MCU_PLL0_HSDIV_CTRL3 Instances

Instance	Physical Address
MCU_PLL0_CFG	0404 008Ch

Figure 5-632 MCU_PLL0_HSDIV_CTRL3 Register

31	30	29	28	27	26	25	24
RESET	RESERVED
R/W-0h	R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
CLKOUT_EN	RESERVED						SYNC_DIS
R/W-0h	R-0h						R/W-0h

7	6	5	4	3	2	1	0
RESERVED	HSDIV
R-0h	R/W-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-1268 MCU_PLL0_HSDIV_CTRL3 Register Field Descriptions

Bit	Field	Type	Reset	Description
31	RESET	R/W	0h	Asynchronous divider reset When set to 1'b1, Internal counters are reset and output clock = 1'b0
30-16	RESERVED	R	0h	Reserved
15	CLKOUT_EN	R/W	0h	CLKOUT0 enable 0h - Synchronously disable CLKOUT0 1h - Synchronously enable CLKOUT0
14-9	RESERVED	R	0h	Reserved
8	SYNC_DIS	R/W	0h	Disable divider synchronization logic 0h - Changes to DIV value synchronized to prevent glitches 1h - Changes are asynchronous
7	RESERVED	R	0h	Reserved
6-0	HSDIV	R/W	0h	CLKOUT0 divider value (HSDIV1+1) Allowed values are 0-127

4.6.3.18 MCU_PLL0_HSDIV_CTRL4 Register (Offset = 90h) [reset = 0h]

MCU_PLL0_HSDIV_CTRL4 is shown in Figure 5-633 and described in Table 5-1270.

Return to Summary Table.

Controls the PLL0 HSDIVIDER4 features and mode of operation.

Table 5-1269 MCU_PLL0_HSDIV_CTRL4 Instances

Instance	Physical Address
MCU_PLL0_CFG	0404 0090h

Figure 5-633 MCU_PLL0_HSDIV_CTRL4 Register

31	30	29	28	27	26	25	24
RESET	RESERVED
R/W-0h	R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
CLKOUT_EN	RESERVED						SYNC_DIS
R/W-0h	R-0h						R/W-0h

7	6	5	4	3	2	1	0
RESERVED	HSDIV
R-0h	R/W-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-1270 MCU_PLL0_HSDIV_CTRL4 Register Field Descriptions

Bit	Field	Type	Reset	Description
31	RESET	R/W	0h	Asynchronous divider reset When set to 1'b1, Internal counters are reset and output clock = 1'b0
30-16	RESERVED	R	0h	Reserved
15	CLKOUT_EN	R/W	0h	CLKOUT0 enable 0h - Synchronously disable CLKOUT0 1h - Synchronously enable CLKOUT0
14-9	RESERVED	R	0h	Reserved
8	SYNC_DIS	R/W	0h	Disable divider synchronization logic 0h - Changes to DIV value synchronized to prevent glitches 1h - Changes are asynchronous
7	RESERVED	R	0h	Reserved
6-0	HSDIV	R/W	0h	CLKOUT0 divider value (HSDIV1+1) Allowed values are 0-127