SPRUJH0B April   2025  – September 2025

 

  1.   1
  2.   Description
  3.   Get Started
  4.   Features
  5.   Applications
  6.   6
  7. 1Evaluation Module Overview
    1. 1.1 Introduction
    2. 1.2 Kit Contents
    3. 1.3 Specification
      1. 1.3.1 External Power Supply or Accessory Requirements
    4. 1.4 Device Information
  8. 2Hardware
    1. 2.1 Hardware Description
      1. 2.1.1 Functional Description and Connections
        1. 2.1.1.1 Power Domains
        2. 2.1.1.2 LEDs
        3. 2.1.1.3 Encoder Connectors
        4. 2.1.1.4 Boot Modes
        5. 2.1.1.5 BoosterPack Sites
        6. 2.1.1.6 Analog Voltage Reference
        7. 2.1.1.7 Other Headers and Jumpers
          1. 2.1.1.7.1 USB Isolation Block
          2. 2.1.1.7.2 Alternate Power
          3. 2.1.1.7.3 5V Step-up Converter
        8. 2.1.1.8 Programmable Gain Amplifier (PGA)
      2. 2.1.2 Debug Interface
        1. 2.1.2.1 XDS110 Debug Probe
        2. 2.1.2.2 Virtual COM Port
      3. 2.1.3 Alternate Routing
        1. 2.1.3.1 Overview
        2. 2.1.3.2 GPIO35/GPIO37 Routing
        3. 2.1.3.3 eQEP Routing
        4. 2.1.3.4 X1, X2 Routing
        5. 2.1.3.5 PWM DAC
    2. 2.2 Using the F28E12x LaunchPad
    3. 2.3 BoosterPacks
    4. 2.4 Hardware Revisions
      1. 2.4.1 Revision A
      2. 2.4.2 Revision E2
  9. 3Software
    1. 3.1 Software Development
      1. 3.1.1 Software Tools and Packages
      2. 3.1.2 F28E12x LaunchPad Demo Program
      3. 3.1.3 Programming and Running Other Software on the F28E12x LaunchPad
  10. 4Hardware Design Files
    1. 4.1 Schematic
    2. 4.2 PCB Layout
      1. 4.2.1 LAUNCHXL-F28E12X Board Dimensions
    3. 4.3 Bill of Materials (BOM)
  11. 5Additional Information
    1. 5.1 Frequently Asked Questions
    2. 5.2 Trademarks
  12. 6References
    1. 6.1 Reference Documents
    2. 6.2 Other TI Components Used in This Design
  13. 7Revision History

2.1.1.1 Power Domains

The F28E12x LaunchPad has several power domains that can be connected or isolated from each other with removable shunts. The different 3.3V and 5V power domains are further described in Figure 2-2.

LAUNCHXL-F28E12X LaunchPad Power Distribution Diagram Figure 2-2 LaunchPad Power Distribution Diagram
LAUNCHXL-F28E12X LaunchPad Power Plane Diagram Figure 2-3 LaunchPad Power Plane Diagram
Table 2-1 describes the usage of the different removable shunts on the LaunchPad board.
Table 2-1 Power Domain Shunts
Shunt Identifier Usage Description
JP1, +5V0 Connects the +5V power from the USB-C connector (+5V0_USB) to the +5-V power on the XDS side of the board (+5V0_XDS110). Bridges the power isolation between the USB and XDS planes.
JP1, GND Connects the board Ground on the isolated USB-C connector side of the board (USB_GND) to the rest of the board ground (GND). Bridges the ground isolation between the USB side and the rest of the board.

JP2, +5V0

 Connects the +5-V power from the XDS side of the board (+5V0_XDS110) to the +5-V power on the MCU side of the board (+5V0_MCU).

JP2, +3V3

 Connects the +3.3-V power from the XDS side of the board (+3V3_XDS110) to the +3.3-V power on the MCU side of the board (+3V3_MCU).
J17 Enables the onboard 3.3V to 5V BOOST regulator to convert the +3.3V power rail to a +5V power rail.

The F28E12x LaunchPad features a flexible power domain scheme that allows users to supply power to the board in a variety of different configurations. Table 2-2 shows the different power configurations and the required shunts that need to be populated to supply power throughout the board.

Table 2-2 Power Configurations
Power Source Connected Shunts Description of Power Sources
USB-C Connector JP1, JP2

+5V0_USB: supplied from the USB-C connector

+5V0_XDS110: +5V0_USB passes through JP1 and is the same supply as +5V0_XDS110

+5V0_MCU: +5V0_XDS110 passes through JP2 and is the same supply as +5V0_MCU

+3V3_XDS110: generated by the XDS-side 5V to 3.3V LDO regulator

+3V3_MCU: +3V3_XDS110 passes through JP2 and is the same supply as +3V3_MCU
External +3.3-V (connected to BoosterPack header) JP2 +5V0 (optional), J17

+5V0_USB: If debugging the device, then connect JP2 +5V0 shunt to provide power to the XDS110 debugger. +5V0_USB is supplied through the USB-C connector and is isolated from the MCU side +5V0 rail. Else if not debugging, +5V0_USB is not required and JP2 +5V0 can be disconnected

+5V0_XDS110: Required only if debugging the device. +5V0_MCU passes through JP2 and is the same supply as +5V0_XDS110

+5V0_MCU: generated by the 3.3V to 5V BOOST regulator

+3V3_XDS110: Required only if debugging the device. +3V3_XDS110 is generated by the XDS-side 5V to 3.3V LDO regulator. Make sure JP2 +3V3 shunt is disconnected to prevent contention on the 3.3V power rail

+3V3_MCU: supplied by external +3.3V source
External +5.0-V (connected to BoosterPack header)

JP2

+5V0_USB: If debugging the device, +5V0_USB is supplied through the USB-C connector and is isolated from the MCU side +5V0 rail. Else if not debugging, +5V0_USB is not required.

+5V0_XDS110: 5V0_XDS110 passes through JP2 and is the same supply as +5V0_MCU

+5V0_MCU: supplied by external +5.0V source

+3V3_XDS110: +3V3_XDS110 passes through JP2 and is the same supply as +3V3_MCU

+3V3_MCU: generated by the XDS-side 5V to 3.3V LDO regulator