SBASAI9 December   2025 ADS122S14

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Switching Characteristics
    8. 5.8 Timing Diagrams
    9. 5.9 Typical Characteristics
  7. 6 Parameter Measurement Information
    1. 6.1 Noise Performance
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Analog Inputs and Multiplexer
      2. 7.3.2  Programmable Gain Amplifier (PGA)
      3. 7.3.3  Voltage Reference
        1. 7.3.3.1 Internal Reference
        2. 7.3.3.2 External Reference
        3. 7.3.3.3 Reference Buffers
      4. 7.3.4  Clock Source
      5. 7.3.5  Delta-Sigma Modulator
      6. 7.3.6  Digital Filter
        1. 7.3.6.1 Sinc4 and Sinc4 + Sinc1 Filter
        2. 7.3.6.2 FIR Filter
        3. 7.3.6.3 Digital Filter Latency
        4. 7.3.6.4 Global-Chop Mode
      7. 7.3.7  Excitation Current Sources (IDACs)
      8. 7.3.8  Burn-Out Current Sources (BOCS)
      9. 7.3.9  General Purpose IOs (GPIOs)
        1. 7.3.9.1 FAULT Output
        2. 7.3.9.2 DRDY Output
      10. 7.3.10 System Monitors
        1. 7.3.10.1 Internal Short (Offset Calibration)
        2. 7.3.10.2 Internal Temperature Sensor
        3. 7.3.10.3 External Reference Voltage Readback
        4. 7.3.10.4 Power-Supply Readback
      11. 7.3.11 Monitors and Status Flags
        1. 7.3.11.1 Reset (RESETn flag)
        2. 7.3.11.2 AVDD Undervoltage Monitor (AVDD_UVn flag)
        3. 7.3.11.3 Reference Undervoltage Monitor (REV_UVn flag)
        4. 7.3.11.4 SPI CRC Fault (SPI_CRC_FAULTn flag)
        5. 7.3.11.5 Register Map CRC Fault (REG_MAP_CRC_FAULTn flag)
        6. 7.3.11.6 Internal Memory Fault (MEM_FAULTn flag)
        7. 7.3.11.7 Register Write Fault (REG_WRITE_FAULTn flag)
        8. 7.3.11.8 DRDY Indicator (DRDY bit)
        9. 7.3.11.9 Conversion Counter (CONV_COUNT[3:0])
    4. 7.4 Device Functional Modes
      1. 7.4.1 Power-up and Reset
        1. 7.4.1.1 Power-On Reset (POR)
        2. 7.4.1.2 Reset by Register Write
        3. 7.4.1.3 Reset by SPI Input Pattern
      2. 7.4.2 Operating Modes
        1. 7.4.2.1 Idle and Standby Mode
        2. 7.4.2.2 Power-Down Mode
        3. 7.4.2.3 Power-Scalable Conversion Modes
          1. 7.4.2.3.1 Continuous-Conversion Mode
          2. 7.4.2.3.2 Single-shot Conversion Mode
    5. 7.5 Programming
      1. 7.5.1  Serial Interface (SPI)
      2. 7.5.2  Serial Interface Signals
        1. 7.5.2.1 Chip Select (CS)
        2. 7.5.2.2 Serial Clock (SCLK)
        3. 7.5.2.3 Serial Data Input (SDI)
        4. 7.5.2.4 Serial Data Output/Data Ready (SDO/DRDY)
        5. 7.5.2.5 Data Ready (DRDY) Pin
      3. 7.5.3  Serial Interface Communication Structure
        1. 7.5.3.1 SPI Frame
        2. 7.5.3.2 STATUS Header
        3. 7.5.3.3 SPI CRC
      4. 7.5.4  Device Commands
        1. 7.5.4.1 No Operation (Read Conversion Data)
        2. 7.5.4.2 Read Register Command
        3. 7.5.4.3 Write Register Command
      5. 7.5.5  Continuous-Read Mode
        1. 7.5.5.1 Read Registers in Continuous-Read Mode
      6. 7.5.6  Daisy-Chain Operation
      7. 7.5.7  3-Wire SPI Mode
        1. 7.5.7.1 3-Wire SPI Mode Frame Re-Alignment
      8. 7.5.8  Monitoring for New Conversion Data
        1. 7.5.8.1 DRDY Pin or SDO/DRDY Pin Monitoring
        2. 7.5.8.2 Reading DRDY Bit and Conversion Counter
        3. 7.5.8.3 Clock Counting
      9. 7.5.9  DRDY Pin Behavior
      10. 7.5.10 Conversion Data Format
      11. 7.5.11 Register Map CRC
  9. 8 Registers
  10. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Serial Interface Connections
      2. 9.1.2 Interfacing with Multiple Devices
      3. 9.1.3 Unused Inputs and Outputs
      4. 9.1.4 Device Initialization
    2. 9.2 Typical Applications
      1. 9.2.1 Software-Configurable RTD Measurement Input
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Performance Plots
        4. 9.2.1.4 Design Variant – 3-Wire RTD Measurement With Automatic Lead-Wire Compensation Using Two IDACs
      2. 9.2.2 Thermocouple Measurement With Cold-Junction Compensation Using a 2-wire RTD
      3. 9.2.3 Resistive Bridge Sensor Measurement With Temperature Compensation
    3. 9.3 Power Supply Recommendations
      1. 9.3.1 Power Supplies
      2. 9.3.2 Power-Supply Sequencing
      3. 9.3.3 Power-Supply Decoupling
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

7.3.11 Monitors and Status Flags

The ADS1x2S14 provide a set of monitors with corresponding status flags to detect and indicate specific device or system faults to the host. Table 7-8 provides an overview of the available monitors. Some monitors need to be enabled using a dedicated monitor enable bit. The monitor fault flags are available in the STATUS_MSB register for readout. If a monitor detects a fault, the according low-active fault flag is set to 0b immediately, even when no conversions are ongoing.

Table 7-8 Monitor Overview
MONITOR NAME MONITOR ENABLE BIT MONITOR FAULT FLAG FAULT FLAG RESET MECHANISM
Reset N/A RESETn Write 1b to clear bit to 1b
AVDD undervoltage N/A AVDD_UVn Write 1b to clear bit to 1b
Reference undervoltage REV_UV_EN REF_UVn Write 1b to clear bit to 1b
SPI CRC SPI_CRC_EN SPI_CRC_FAULTn Updates in every new SPI frame based on the CRC result of the previous SPI frame
Register Map CRC REG_MAP_CRC_EN REG_MAP_CRC_FAULTn Write 1b to clear bit to 1b
Memory Map CRC N/A MEM_FAULTn Reset or power-cycle the device
Register Write Fault N/A REG_WRITE_FAULTn Updates with the next register write command

In addition to the monitors, a data ready indication bit (DRDY) is available in the STATUS_MSB register, and a 4-bit conversion counter in the STATUS_LSB register.

Instead of reading the STATUS_MSB or STATUS_LSB registers on demand using a register read command, the devices can output a STATUS header as the first two bytes of every frame on SDO. Enable the STATUS header transmission using the STATUS_EN bit. The 16-bit STATUS header is a concatenation of the STATUS_MSB[7:0] and STATUS_LSB[7:0] register bits.